如何创建坚固和可靠的FPGA设计- 爱特公司厂商_在线座谈

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主题:如何创建坚固和可靠的FPGA设计
在线问答:
[问：Philips]	请问如何解决FPGA上电过程中I/O管脚状态的不确定性对与FPGA互连器件的影响？
[答：Albert]	This only happens to SRAM FPGA, Actel"s anti-fuse and Flash FPGA does not have this problem. Because our FPGAs are live at power up, they don"t need to wait for the downloading of bitstream, so their I/O states are stable upon power up.	[2003-12-19 10:39:10]
[问：lixuemei]	请问：用FPGA实现算法时，如何能提高速度？用Verilog HDL谢谢！
[答：Albert]	You may use dedicated macro generator (e.g. multiplier or adder). The macro generator from Actel is called Actgen	[2003-12-19 10:39:27]
[问：yczh2004]	如何才能提高对于FPGA/CPLD设计的效率,避免出现毛刺和倾斜?
[答：Albert]	If you follow synchronous design guidelines I mentioned in this presentation, you will be able to solve the glitch and skew problems	[2003-12-19 10:39:44]
[问：samire]	如果有多个时钟输入,FPGA如何处理?如何分布?
[答：Albert]	It depends on whether these clocks are inter-related. For non-related clocks, you may route them with individual global clocks. Otherwise, you need to be very careful in planning their timing during syncrhonization	[2003-12-19 10:40:05]
[问：yuxun.china]	如何对FPGA的配置文件加密？
[答：Albert]	Our Flash FPGA has a very secure feature, which allows you to encyrpt the programming file with a security key	[2003-12-19 10:40:49]
[问：安子]	请问专家,对于FPGA器件,如果器件的某个部分被损坏了,其余完好的部分是不是还能正常工作,因为我们知道FPGA各个部分的结构是相同的.如果一部分坏了可以将这部分的程序(VHDL)移到别的部分正常运行么?
[答：Albert]	I won"t recommend you to do so, as you will not know exactly which part of the FPGA is damage.	[2003-12-19 10:41:24]
[问：ecnan jing_EBY7E]	vhdl 中结构体描述中的行为描述，结构描述，寄存器传输描述有什么不同啊？
[答：Albert]	Behavioral modeling is high level modeling technique, which is best for describing complicated behavior. But it is not 100% synthesizable.RTL modeling is guaranteed to be synthesizable.	[2003-12-19 10:42:50]
[问：szliu]	使用fpga设计时，使用异步逻辑需要注意些什么？谢谢！
[答：Albert]	You need to make sure that the asynchronous logics do not feed the clock input of all flip-flop	[2003-12-19 10:43:24]
[问：xzzss]	如何才能消除设计过程中产生的毛刺对逻辑功能的影响？有那些FPGA器件可以输入模拟信号呢
[答：Albert]	It is not possible to eliminate all glitchs in a design, however as long as the glitchy signal does not feed the regsiters" clock input, then it is fine.As far as I know there is no FPGA can accept analog signal input at the moment.	[2003-12-19 10:46:04]
[问：sunys]	用FPGA实现与DSP(例如ADSP2106)相同的信号处理程序（例如FFT4096点），系统设计的难度（硬件调试和软件编程）是否更大．
[答：Albert]	Implementing DSP in FPGA requires special EDA tools to translate the algorithm into RTL code. Some EDA vendor in the market like Synopsys, Cadence are Mentor providing these product.	[2003-12-19 10:47:22]
[问：Philips]	如何才能消除设计过程中产生的毛刺对逻辑功能的影响？
[答：Albert]	Glitchs in a design only have bad effect if they are connected to clock. If you follow the synchronous design guidelines I mentioned in the presentation, those gliches won"t harm you.	[2003-12-19 10:48:57]
[问：chinawml]	在FPGA的实际设计中，可能会出现这样的情况：由于某种原因使得管脚的输出错误，重新将程序写芯片，就会使管脚输出正常.请问FPGA中的资源是否能够在设计文件中进行定位，也就是说达到门级的对应？能否进行人为的调整，使程序的资源配置更优化？谢谢。
[答：Albert]	The case you mentioned is mostly due to unstable design, which has potential timing problem.On the other hand, you can do manual placement of logic cell in a FPGA. But it is unlikly that the result will be more optimized than the result done by the software	[2003-12-19 10:50:44]
[问：ljp]	采用这种设计,FPGA的资源利用率有多高?
[答：Albert]	It mostly depends on the complexity and methodology of your design. Synchronous design sometimes require more logics than asynchronous design, but it is also more reliable and robust.Reliability is the first priority for FPGA design!	[2003-12-19 10:52:25]
[问：samire]	在FPGA设计中,如何控制同步时钟的数量?它在FPGA中如何分布才更合适?
[答：Albert]	Only the designer can control the number of clock in a design. For a 100% synchronous design, there will only be 1 clock.For multi-clock designs, it is suggested that these clocks be routed on global clock resource	[2003-12-19 10:53:45]
[问：doven2000]	FPGA器件时钟的引入问题；通过I/O和通过规定的时钟端口两钟方法各有什么不同的特点？
[答：Albert]	For normal input pin, the clock will experience longer input delay. Normal input pin also has lower internal fan-out limit, and will need to be buffered. Dedicated clock pins normally connected to global clock networks, and do not have this problem	[2003-12-19 10:55:05]
[问：liwenz]	FPGA和DSP通过DSP的地址线和数据线进行数据交换，需要注意什么？谢谢
[答：Albert]	You need to pay attention to the I/O timing of the DSP"s address and data bus, and design your FPGA to synchonize with them. Normally DSP provides read/write control signals, you may use these signals to access them	[2003-12-19 10:56:39]
[问：willam_gann1]	请问，如何在一个fpga中实现两个时钟的协调工作？
[答：Albert]	It very much depends on how these two clocks interact with each other. There is no single solution to it....	[2003-12-19 10:57:28]
[问：amaosonic]	请问FPGA设计中，就只能运用全局时钟来控制了吗？若是需要用到两个时钟呢，怎么来设计才能消除时钟倾斜和毛刺？
[答：Albert]	Please refer to the presentation I have mentioned. I have convered the solutions to your questions	[2003-12-19 10:58:27]
[问：xue_fly]	在FPGA的设计中，怎样处理好两个时钟域之间交换数据时带来的多稳态问题？
[答：Albert]	Normally we use one or two levels or flip-flop bewteen two clock domains to reduce the effect of metastable by synchronizing the data from one clock domain"s output with another clock from another clock domain	[2003-12-19 11:00:03]
[问：paradbird]	请问如何解决两个时钟交界处数据的同步？
[答：Albert]	Please refer to my answer to the same question I have just answered	[2003-12-19 11:00:33]
[问：lihongwx]	为何有时用原理图设计可以正常工作，而用VHDL设计则出现时序混乱。如何避免此情况？
[答：Albert]	HDL is less intutive than schematic, sometime inappropriate logic may be generated by without paying attention to the coding style.	[2003-12-19 11:02:13]
[问：wzjjw]	你曾提到通过增加Rigister-Register延迟来满足Clock Skew的问题，但是增加R-R延迟，则整个电路的时钟工作频率不会很高，如何减少Skew应该是关键吧？
[答：Albert]	Yes, you"re right! That"s why I said synchronous design is so important	[2003-12-19 11:03:43]
[问：linckcheng]	一個同步電路,如何避免每一次電路修改及重新編程後時序結果不相同的問題
[答：Albert]	This happens to asynchronous design. Or sometime, even if the design is synchronous, but you haven"t verified the timing in different working conditions (best/typical/worse) you might omit some potential timing problems	[2003-12-19 11:05:19]
[问：willam_gann1]	我现在在用你们的lh7a400 EVB ,有些功能我们不要了，想在原来的GPIO把它改为他用，请问如何修改源代码（系统是LINUX）。你们随光碟里的一些DRIVE源代码是作什么用的。谢谢！
[答：Albert]	I think it is not our product....	[2003-12-19 11:05:52]
[问：kadial]	完全同步的设计，在速度很高的情况下，也会出现毛刺，请问，如何避免这样的毛刺的出现
[答：Albert]	Glitch occurs no regardless of the clock frequency. As I said, the main point is not to avoid glitch. It is more important to note that those glitchy signals do not feed registers" clock inputs	[2003-12-19 11:07:05]
[问：hwyuyu]	1.在国内很难买到贵公司的带FLASH的FPGA,贵公司在那些地方有分销商,怎么联系?2.带FLASH的FPGA的运行速度是否和不带FLASH的一样,还是快?3.Actel的Libero 5.0 是否免费?不免费,价格多少?4.Actel的下载电缆是否专用?还是象Xilinx,Altara等公司公开其下载电缆电路原理图.
[答：Albert]	We have two distributors in China, you may contact them (Secom and Unique) for more details.Our download capable is not compatible with those provided by Xilinx and AlteraLibero has two free (Silver and evaluation) version that you may download it from our web or contact our distributors	[2003-12-19 11:09:08]
[问：clydefang]	Actel公司是否提供实现DSP转换到FPGA的第三方工具？
[答：Albert]	I"m sorry that we don"t....	[2003-12-19 11:09:23]
[问：fyx123]	Hello Mr.Dai.When will the 5.1 released? I want to get it!What new character it has than the old? Thanks!
[答：Albert]	Libero 5.1 has just been relesed, it is available now. Please refer to the release note for new features in this version.	[2003-12-19 11:10:54]
[问：scanli]	在市场上有没有能解密ACTEL的EPGA的服务？
[答：Albert]	Actel"s FPGA is the most secure FPGA in the world. I have not heard any company can hack our product in the market.	[2003-12-19 11:11:48]
[问：xzzss]	请问如何解决FPGA上电过程中I/O管脚状态的不确定性对与FPGA互连器件的影响
[答：Albert]	If you use our anti-fuse or flash FPGA, you won"t have this problem because our devices are live at power up, their I/O state are stable upon power-up	[2003-12-19 11:12:31]
[问：lihongwx]	actel的FPGA功耗是多少？上电是是否会有瞬间的电流冲击？
[答：Albert]	The power consumption is design and clock frequency dependent. But, in general, antifuse and flash FPGA has lower power consumption when compared to SRAM FPGA fabricated with the same process. We don"t have power up surge current! It is the SPECIAL FEATURE of SRAM FPGA only ;)	[2003-12-19 11:14:25]
[问：caishang]	请问哪些软件对Actel器件的支持较好？能推荐一些仿真综合的软件吗？
[答：Albert]	Synlicity (for synthesis) and Modelsim (for simulation)	[2003-12-19 11:14:54]
[问：zf_fan]	关于程序的稳定性验证问题。有没有自动的工具？ｌｉｂｅｒｏ　５．０有没有一些仿真验证的工具？
[答：Albert]	The back-end tools of Libero 5.0, Designer has a function call Timer, which can assist you to locate the potential timing problem.Libero enclose ModelSim for simulation purpose	[2003-12-19 11:16:07]
[问：zhuoyue]	actel的fpga在dll或pll方面有什么特点
[答：Albert]	Please refer to our datasheet for more details about the electrial characteristic of the PLL in APA and AX.For APA, its PLL is dynamically configurable without changing the whole design and re-place & route	[2003-12-19 11:17:31]
[问：lihongwx]	在FPGA中如何实现MCU？如何操作MCU内核？
[答：Albert]	You may purcahse the MCU IP and then put it in a FPGA. There are quite a lot of MCU IP in the market. Actel and its IP partners also provide a range of different MCU IP (like 6809, 8051, etc). Please refer to our webpage for more details	[2003-12-19 11:19:06]
[问：lihongwx]	actel的FPGA可以实现的ram有多大？
[答：Albert]	It depends on the family. APA family has 198Kbit and AX has around 300Kbit	[2003-12-19 11:19:41]
[问：amaosonic]	麻烦介绍一下多稳态吧
[答：Albert]	Metastable occurs when a flip-flop can not meet its setup/hold time requirements. The output is not stable and not determined. The unstable period depends on how much the setup/hold time violation is.	[2003-12-19 11:21:24]
[问：lihongwx]	哪里可以得到actel的设计软件？
[答：Albert]	You may either contact our distributor in China (SECOM or Unique), or you may go to our website to download it.	[2003-12-19 11:22:03]
[问：whhjwl]	ProASIC plus系列中的PLL锁相频率范围非常宽，除了可以做分频倍频等时钟合成外，请问是否适合做串行通讯中的Clock & Data Recovery
[答：Albert]	Yes, it can be used in CDR applications	[2003-12-19 11:22:29]
[问：caishang]	请问你演讲用到的软件名称？
[答：Albert]	Libero 5.1	[2003-12-19 11:22:59]
[问：qin]	能否对同步时钟进行仿真?需要什么软件?仿真的效果如何?是在电路中进行的吗?
[答：Albert]	Of course you can. We will recommend ModelSim. It is a third party tool. Actel IDE Libero 5.1 integrate Modelsim	[2003-12-19 11:24:03]
[问：qin]	贵公司的FPGA中是否有PLL单元?有几个?每个的输出端有几个?频率能达到多高?
[答：Albert]	Yes, our APA and AX families have PLL. For detailed specification, please refer to the datasheet, they can be downloaded from our website:www.actel.com	[2003-12-19 11:24:57]
[问：amaosonic]	请问怎么利用retiming技术来优化FPGA同步设计设计的性能呢/
[答：Albert]	Some EDA tools (like Synplify pro) support automatic retiming feature. Manual retiming is time consuming and subject to careless mistakes!	[2003-12-19 11:26:24]
[问：sfm7739]	actel的fpga内部dll可以倍频到多高频率，具体器件是什么？
[答：Albert]	Our APA and AX families have internal PLL (not DLL), for detailed specification, please refer to their datasheets that can be download from our website:www.actel.com	[2003-12-19 11:27:21]
[问：doven2000]	当用I/O口输入时钟时，如何减少毛刺？谢谢！
[答：Albert]	The most important thing is not to use a low slew rate clock input (e.g. from crystal output). Dedicated oscillator chip is recommended.	[2003-12-19 11:28:22]
[问：zhuoyue]	actel的fpga与xilinx，altera的相比有那些特点和优势
[答：Albert]	We are more secureWe are live at power upWe are lower power consumingWe are more reliableAnd more..	[2003-12-19 11:29:09]
[问：gk.h]	在flash fpga中每次编译后结果相差比较大，是什么原因？不知到可不可以在编译时将原来的固定，只编译修改过的地方呢？
[答：Albert]	You may use incremental P&R to reduce the variation between different P&R runs.	[2003-12-19 11:30:07]
[问：ljp]	如何确定时钟频率和时钟偏斜的最佳关系?抖动关系呢?
[答：Albert]	Skew has to be less than the reg-reg delay - hold timeYou"re right the above relationship does not consider clock jitter. With jittered clock, you should also subtract the maximum jitter from the right hand side of the equation	[2003-12-19 11:32:27]
[问：lileiming888]	对于同步电路，有没有建立时间，保持时间不够的亚稳态状态？
[答：Albert]	Yes, it also has these problems. However it only happen when the target clock frequency can not be met. So if the clock frequency is met, you won"t see these problem (for a 100% synchronous design)	[2003-12-19 11:33:54]
[问：gk.h]	actel的fpga的编程时间都比较长，不知道有什么好的办法？
[答：Albert]	You may use multi-site programming to increase the run rate during mass production	[2003-12-19 11:35:36]
[问：Wizard]	使用EPROM对FPGA进行配置时如何达到最快的速度?
[答：Albert]	We don"t need to use EPROM to configure our FPGAs	[2003-12-19 11:36:17]
[问：lileiming888]	对于同步电路来说，假设数据都是在时钟沿上升时改变，这和要求的固定建立时间，保持时间有矛盾吗？
[答：Albert]	No, it won"t, because the changed data will be clocked in the next rising edge, and thus will not have setup/hold time problem. But asyncrhonous design will have this problem	[2003-12-19 11:38:07]
[问：m-2-m]	FPGA与CPLD的最大区别是什么？应用场合有不同吗？
[答：Albert]	FPGA is more flexible, usually has more routing resource. CPLD has small gate count and is not suitable for complicated designs.	[2003-12-19 11:39:14]
[问：myatmel]	actel的FPGA是可以加密的，如果，我自己的程序，多次烧录芯片后，不小心将密码忘记了，有没有解决的办法。
[答：Albert]	Which family is it? For flash FPGA, if you haven"t turned on the permanent key feature, you may send the chip back to Actel, we can help you. Otherwise, we can"t, it is so secure that even we cannot unlock it in this case	[2003-12-19 11:40:48]
[问：zzycat]	请问贵公司的FPGA和XILINX,ALTERA公司的FPGA比较，有那些优缺点？
[答：Albert]	We are more secureWe are live a power upWe has lower power consumptionWe are more reliableMany more...	[2003-12-19 11:41:28]
[问：zhengbh]	您好！请问FPGA系统对系统时钟有何要求？我有一个90MHz的晶振，正弦波，与用方波相比有何不同
[答：Albert]	It is not recommened to feed a FPGA"s clock with crystal output (sine wave), it will cause internal glitch after pass through the input buffer. Our APA devices has input Schmitt trigger input that can help to reduce this problem	[2003-12-19 11:43:17]
[问：Philips]	请问一下，在FPGA设计中怎样可以使得芯片资源利用率提高？
[答：Albert]	The problem is situation dependent. For example, in our eX/SXA family, you may use two C-cell to implement a flip-flop, so in case dedicate is not enough, you may use this approach to increase the utilization	[2003-12-19 11:44:42]
[问：gk.h]	你们apa系列的flash fpga中的pll是否主要是处理相位的，我用它作时钟提取时，发现提取出的时钟抖动非常大，是什么原因？
[答：Albert]	If the jitter in the input clock is too big it will lost tracking and produce big jitter at the output	[2003-12-19 11:46:06]
[问：whhjwl]	针对有很多小的分散存储器的应用，APA系列的Embeded RAM Blocks显得每块尺寸太大，块数又太少。而Xilinx的CLB可转换为16x1的小RAM，这一点很灵活。尽管这是SRAM based FPGA先天的优点，但我们很希望用非易失的FPGA，不知Actel有何建议？
[答：Albert]	We will increase the number of RAM in our next generation flash FPGA	[2003-12-19 11:46:54]
[问：leeskycau]	FPGA的功耗怎样计算？和CPLD相比，设计上需要注意那些细节？谢谢！
[答：Albert]	Power consumption has two parts, static and dynamic. Actel FPGAs have much lower dynamic power consumption than CPLD	[2003-12-19 11:48:32]
[问：lyjsolar]	时钟偏斜和时钟延迟有什么联系和区别？
[答：Albert]	Clock skew is the diffence in clock delay between different registers.	[2003-12-19 11:49:32]
[问：lyjsolar]	时钟偏斜主要有什么引起的？时钟延迟呢？如果我想增加延迟一般怎么做？再fpga内部？
[答：Albert]	Clock skew is caused by wide spreading clock delay. Global clock network in FPGA can be used to address the clock skew problem. It is not recommended to add buffer to tune clock delay. It is asynchronous design style and is hard to control the delay after place & route	[2003-12-19 11:51:18]
[主持人：ChinaECNet]	恭喜您，烽火通信科技股份有限公司的 qzhu！经过电脑抽奖您在本次座谈中获得一部MP3播放器。请网名为 qzhu 的用户与中电网联系(8610-82888222-7009 或 lilin@chinaecnet.com)。	[2003-12-19 11:52:07]
[问：linckcheng]	在電路設計中,使用上一級Register的輸出直接作為激發下一級Register的CLK,如果確定其間无任何Combinational電路,請問是否還是會有CLK毛刺問題?
[答：Albert]	In this case, it won"t. But you have to make sure that the ouput of these two registers are not used in other places of your design.	[2003-12-19 11:52:09]
[主持人：ChinaECNet]	现在座谈即将结束。欢迎各位填写在线座谈页面的问卷调查，并请于明天中午12点以前提交。提交调查的用户将有机会获得中电网的小礼品一份。	[2003-12-19 11:52:20]
[问：qzhu]	Actel的对图形化设计支持兼容性如何.
[答：Albert]	Our Libero IDE design environment consists a schematic tools call Viewdraw	[2003-12-19 11:52:50]
[主持人：ChinaECNet]	由于时间关系，本次中电网“在线座谈”马上就要结束了。今天虽然各位听众（网友）已与Actel公司讨论了许多问题，但是还有许多提问没有来得及进行交流。本次在线座谈结束后，中电网将请Actel公司的专家继续答复所有的来自各位听众（网友）的提问，然后整理上载到中电网网站上，以便大家查阅。	[2003-12-19 11:53:12]
[主持人：ChinaECNet]	在此，中电网特别感谢给予本次中电网在线座谈巨大支持的Actel公司，特别感谢专门在线回答各位听众（网友）提问的Actel公司的各位专家们，特别感谢各位听众（网友）积极热情的参与。	[2003-12-19 11:53:30]
[主持人：ChinaECNet]	祝大家事业有成、生活愉快！欢迎多提宝贵意见，欢迎关注中电网，下次再见。	[2003-12-19 11:53:47]

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