在线座谈

热门关键字: DaVinci EAM ANSI DSL 

关于本次座谈

座谈简介

本机振荡器一直被广泛使用在无线基础设施、调谐器和ADC/DAC时钟等设备中。而大多数这些应用要求本机振荡器必须可调。因此,在这次研讨会中,我们将关注VCO即压控振荡器。如果没有控制,VCO的频率会产生漂移,锁相环用于将VCO锁定在所需的频率上;因此,当谈到本机振荡器时,我们是指整个PLL和VCO系统设计。我们也会在研讨会中谈到在设计本机振荡器时需要考虑的参数,包括环路带宽、相位余量、锁定时间和寄生干扰对于诸如充电泵电流、N计数器值、相位检测器频率等。

精彩问答

主题:本机振荡器的特性和设计要素
在线问答:
[主持人:ChinaECNet] 各位听众(网友),上午好!欢迎参加中电网在线座谈。今天,我们有幸邀请到美国国家半导体公司的专家就“本机振荡器的特性和设计要素”举行在线座谈。在座谈中,您可就您关心的问题与美国国家半导体公司的专家在线进行直接、实时的对话交流。中电网衷心希望通过大家的共同努力,不仅能够增进各位听众(网友)对“本机振荡器的特性和设计要素”的了解和掌握,而且能够为大家事业的发展带来裨益。  [2007-11-29 10:11:09]
[问:tocoo] 对于相位噪声,我们知道环路很窄,会出现肩膀,这样的情况在尽量不改变环路的情况下。怎么处理? 
[答:Noel Fung] What did you mean of 怎么处理?  [2007-11-29 10:24:10]
[问:tocoo] 怎么理解推挽系数,他们对频综的作用是什么? 
[答:Noel Fung] Both pushing or pulling effect will change the free running frequency of the VCO, that is why you"ll need a PLL to maintain the desired frequency  [2007-11-29 10:26:05]
[主持人:ChinaECNet] 我们已经进入问答阶段如果听众想重温演讲或内容可以点击下面“回顾演示”重看演讲。  [2007-11-29 10:27:13]
[问:tocoo] 请问一般看锁定时间是怎么看的?你们是看几Hz内算锁定。 
[答:Shawn Han] The lock time is defined as the time that it takes for the PLL to change from one frequency to another to a given tolerance. The tolerance bases on your system requirement.  [2007-11-29 10:27:41]
[问:weslin9] vco现在有哪些比较好的处理芯片? 
[答:Noel Fung] Did you mean PLL? Selection of PLL is application specific. For example, integer-N or fractional-N PLL; is fast frequency switching required?; single or dual PLL, etc  [2007-11-29 10:28:12]
[问:tocoo] 在选择环路滤波器的时候,我们现在一般用的是三阶的,然后我想问的是中间的两个时常数电阻一般怎么选择? 
[答:Robert Shen] 可以用我们网上在线设计工具:http://webench.national.com/appinfo/wireless/webench/index.cgi  [2007-11-29 10:28:34]
[问:tocoo] 目前我在用你们的LMX2326的时候,经常会遇到损坏,表现为参考输入没有,量电压只有零点几V,请问这一般是哪里坏了?原因是什么? 
[答:Janet Wu] 您说的损坏是指芯片已经被烧毁吗?请将您遇到的具体现象记录下来,并且联系我们的技术支持寻求帮助。我们将根据您的具体现象进行分析,从而研究原因。您可以在这个URL联系技术支持:http://www.national.com/CHS/support/.  [2007-11-29 10:29:43]
[问:zstone512] 为什么环路带宽在设计时设定为步进的十分之一 
[答:Noel Fung] this rule is applied to integer-N PLL only, there isn"t limitation to fractional-N PLL.  [2007-11-29 10:30:17]
[问:zxh720217] 如果我想实现零角度的相位跟随,有什么比较好的方案呢?跟踪频率可以是几百K,如果要提高频率的话可以到多少呢? 
[答:Noel Fung] phase error always exist, the question is how much it is. So, in order to reduce phase error, integrated phase nose must be low. One of the methods is to use a wide loop bandwidth filter.  [2007-11-29 10:32:30]
[问:tocoo] 请给我们清晰的讲解一下,相位余量跟环路之间的关系吧? 
[答:Shawn Han] 相位余量偏移0度越远,环路越稳定,一般在设计在几十度  [2007-11-29 10:33:06]
[问:radar] NS介绍的本机振荡器,是正弦波还是方波输出? 
[答:Janet Wu] 正弦波输出。  [2007-11-29 10:33:12]
[主持人:ChinaECNet] 各位观众,现在用户提问很踊跃,专家正在逐一回答。请耐心等待您问题的答案,同一问题请不要多次提交。  [2007-11-29 10:33:14]
[问:qiaopeng] 您好,我刚刚开始做射频前端的电路设计,请问在射频收发信机中选择VCO芯片时应该主要考虑哪些参数呢?它们对系统的影响是怎样的? 
[答:Shawn Han] 频段覆盖范围,供电电源,调谐电压范围,Kvco,相位噪声等  [2007-11-29 10:34:49]
[问:damihuang] 如何购买NS公司的VCO?有无样片提供? 
[答:Janet Wu] 您可以到我们公司网站www.national.com进行搜索,进到具体产品的页面中,可以在线申请样片。  [2007-11-29 10:34:55]
[问:tocoo] 遇到寄生跟相噪两个平衡问题,一般怎么处理? 
[答:Noel Fung] This is application specific, spurs or phase noise, which one is more important. Also, it depends on which type of PLL, integer-N or fractional-N. Fractional-N PLL offers you more flexibility to reduce spurs and phase noise  [2007-11-29 10:35:06]
[问:蒋源明] 还未使用过国半的产品,请推荐可以使用在Bluetooth产品中的VoS,还有其相位噪声和调谐线能达到什么水平。 
[答:Robert Shen] 我们有Simple Blue, 可以用于Bluetooth的应用。如LMX9830. 可以到我公司网站查询。http://www.national.com/pf/LM/LMX9830.html  [2007-11-29 10:35:16]
[问:qiaopeng] 请问在一般的无线通信系统中(如对讲机),只采用VCO是否可以达到需要的频率稳定度,还是必须采用VCO+PLL的结构? 
[答:Shawn Han] 使用PLL+VCO作为本振  [2007-11-29 10:35:43]
[问:shijh] 请问,如何减小或消除本机振荡器的相位噪声? 
[答:Noel Fung] Usually, a wide loop bandwidth filter will reduce the overall phase noise  [2007-11-29 10:36:21]
[问:sduboy] 请问国家半导体在本机振荡器方面有哪些相关解决方案? 
[答:Janet Wu] 请首先参见我们在演讲中提到的一些产品,另外您也可以到我们网站上查找更多信息。如果对选择产品有任何疑问,欢迎您联系美国国家半导体的技术支持:http://www.national.com/CHS/support/  [2007-11-29 10:36:42]
[问:radar] NS有哪些本机振荡器的解决方案? 
[答:Robert Shen] 有很多PLL方案供选择,详见:http://www.national.com/appinfo/wireless/  [2007-11-29 10:37:13]
[问:sduboy] 产生寄生干扰的因素有哪些? 
[答:Noel Fung] we mentioned that there are two types of spurious, depending of the type of PLL. Pls review the seminar again.  [2007-11-29 10:37:34]
[问:weiliya] 体质多大? 
[答:Janet Wu] 请具体描述您的问题,谢谢!  [2007-11-29 10:37:35]
[问:sduboy] 设计本机振荡器时如何有效减少可能产生的误差? 
[答:Noel Fung] what error did you mean?  [2007-11-29 10:37:59]
[问:sduboy] 导致VCO的频率产生漂移的原因是什么? 
[答:Noel Fung] at the begining of the seminar, we introduced several reasons why a VCO will drift if without control, pls review the seminar again  [2007-11-29 10:38:57]
[问:chenrong713] 我是学通信的 ,但是了解的东西很少,不太知道一些专用名词,请问充电泵的构成是什么?它是一个提供电路用电流的充电系统吗? 
[答:Shawn Han] Charge Pump将误差电压转换为电流输出,给环路滤波器提供电流,以调谐VCO  [2007-11-29 10:39:17]
[问:mhjuan119] 请问这种振荡器主要用于哪些方面,与其他振荡器相比有什么特点? 
[答:Robert Shen] 主要用于通讯。NS的产品丰富覆盖面广。  [2007-11-29 10:39:21]
[问:hnldxhlfch] 可调振荡器中的晶体振荡器的特殊性是什么? 
[答:Shawn Han] VCO受到调谐电压控制  [2007-11-29 10:39:46]
[问:sduboy] 锁定时间对本机振荡器性能的影响是什么? 
[答:Noel Fung] This is application specific. For example, in TDD system, lock time is important. In FDMA system, lock time may not be a concern  [2007-11-29 10:39:53]
[问:damihuang] NS公司有无集成VCO的PLL芯片?性能指标和独立VCO有无明显差距? 
[答:Robert Shen] 有,如LMX2531:http://www.national.com/pf/LM/LMX2531LQ1700E.html  [2007-11-29 10:40:33]
[问:fk988] 本机无源振荡器设计的难点及解决方法 
[答:Noel Fung] I don"t think there exist passive LO. The engery storged in the resonant circuit will be loss at time goes by. You need an active device to maintain the oscillation  [2007-11-29 10:41:49]
[问:sduboy] 本机振荡器有哪些类型? 
[答:Robert Shen] 在通讯应用中绝大多数用PLL。也有用频率合成的,但也要用到PLL。  [2007-11-29 10:42:54]
[问:whappin] VCO的频率会产生漂移究竟会对本机震荡器在实际应用中产生怎样的影响? 
[答:Noel Fung] if the drift is very serious, the tuning voltage to maintain it to operate at a certain frequency may vary a lot. If this voltage exist the capability of the PLL, you will loss lock  [2007-11-29 10:43:31]
[问:sduboy] 能否简要介绍一下本机振荡器在无线基础设施中的应用? 
[答:Shawn Han] 一般用于发射与接收通道中的中频本振和射频本振,属于无线通信设施中的心脏电路。  [2007-11-29 10:43:58]
[主持人:ChinaECNet] 各位观众,现在用户提问很踊跃,专家正在逐一回答。请耐心等待您问题的答案,同一问题请不要多次提交。  [2007-11-29 10:45:13]
[问:whappin] 寄生干扰对N计数器值等的危害性是"致命"的吗? 
[答:Noel Fung] the spur will increase the overall integrated phase noise. even though the phase noise is low, but if you have a high spur, the overall integrated noise will be high and you"ll get high phase error  [2007-11-29 10:45:20]
[问:sduboy] 请问从哪些方面可以提高本机振荡器的性能? 
[答:Robert Shen] 如本文提到的,降低噪声,抑制杂散等。  [2007-11-29 10:45:37]
[问:elegance9527] 振荡器的时间抖动(jitter)在仿真的时候用什么方法测试? 
[答:Shawn Han] Jitter是相位噪声在一定频带内的积分,可以使用带jitter测试的频谱分析仪测试,或者测得相位噪声后,手工估算积分。  [2007-11-29 10:46:10]
[问:BB1234] 1. 若要进行模拟测试,有什么设计工具可供采用? 
[答:Robert Shen] 我们网上设计工具:http://webench.national.com/appinfo/wireless/webench/index.cgi  [2007-11-29 10:46:26]
[问:sundong] 应该为 f=1/2π(LC)1/2 
[答:Noel Fung] that depends on whether the unit is in radian or degree  [2007-11-29 10:46:39]
[问:elegance9527] 时间抖动(jitter)在仿真的时候用什么方法测量? 
[答:Janet Wu] 请参见我们的演讲资料中第23页的具体描述。  [2007-11-29 10:47:42]
[问:radar] NS介绍的本机振荡器在成本和性能上有什么优势? 
[答:Robert Shen] 品质好,噪声低,体积小,性价比高。  [2007-11-29 10:48:30]
[问:BB1234] 可否谈一谈有关3级有源滤波器的设计方法? 
[答:Betty Lee] We would recommend you to read the following book.  Pls download it from http://www.national.com/appinfo/wireless/pll_designbook.htm  [2007-11-29 10:48:40]
[问:lanlaneer] 如何根据需要的本机振荡器的精度来选择其架构,能不能具体的举个例子 
[答:Noel Fung] simply speaking, fractional-N PLL can give you the highest frequency resolution. In addition, the accuracy or stability of the TCXO also affect the overall accuracy. At last, care must be paid on the charge pump leakage  [2007-11-29 10:48:42]
[问:weslin9] 设计本机振荡器时需要考虑哪些参数,它们具体是怎么影响器件性能的? 
[答:Noel Fung] I recommend you review the whole seminar  [2007-11-29 10:49:02]
[问:BB1234] 可否采用锁相环路将压控晶体振荡器锁定? 
[答:Robert Shen] 是的,PLL的原理是这样。  [2007-11-29 10:49:21]
[问:mhjuan119] 请问这种振荡器主要用于哪些方面,与其他振荡器相比有什么特点? 
[答:Janet Wu] 一般用于发射与接收通道中的中频本振和射频本振,属于无线通信设施中的心脏电路。  [2007-11-29 10:50:02]
[问:gpnww131] 环路带宽的计算公式 
[答:Noel Fung] it is very complicated, I recommend you visit wireless.national.com, we have a book written by our application engineer, the book introduced all the calculation  [2007-11-29 10:50:07]
[问:lanlaneer] 在我们使用本机振荡器时,应该根据什么参数来进行选择才能使其工作在最优状态 
[答:Shawn Han] 目前设计频率合成器电路最多的调试工作在调整环路滤波器,这是一个相位噪声,锁定时间,相位余量等多个参数的折衷,建议仿真获得最优参数。国半网站上有在线仿真工具:http://www.national.com/appinfo/wireless/webench/  [2007-11-29 10:50:10]
[问:閆繼偉] 怎樣更有效的解決振荡器所產生的尖峰對EMI造成的問題 
[答:Noel Fung] I think they are two different things. EMI concerns the overall emissions. for example, emission from the antenna, pcb or wires. As long as you shield the VCO properly, usually, it will not create EMI issues  [2007-11-29 10:51:43]
[问:weslin9] 本机振荡器在无线通讯应用中有哪些优势? 
[答:Shawn Han] 基本上是必选件。国半在本振电路设计上有着很悠久的历史。  [2007-11-29 10:52:21]
[问:smilings] 小数分频的缺点是什么? 
[答:Janet Wu] 主要有剩余调制和振动性能不好  [2007-11-29 10:52:31]
[问:diandianxin2007] 本机振荡器与其他同类产品相比更具有什么优越性? 
[答:Robert Shen] 稳定,可靠,设计简单。  [2007-11-29 10:52:31]
[问:nnyy0011] 一般的PLL用Cadence软件如何仿真他的jitter噪声呢? 
[答:Shawn Han] Cadence仿真高速数字信号有优势,PLL仿真可在国半网站上进行http://www.national.com/appinfo/wireless/webench/  [2007-11-29 10:53:26]
[问:whappin] 刚才讲到,若无控制,频率漂移严重.这种控制的实现手段和方法能否再详细介绍一下,谢谢! 
[答:Noel Fung] For the VCO itself, (1) you have to maintain a fixed loading to the VCO, this will reduce frequency pulling. For example, add a buffer amplifier after the VCO. (2) for frequency pushing, the Vcc to the VCO is better supplied from a low noise LDO, for example, LP5900. For the overall system, you will need a PLL  [2007-11-29 10:54:16]
[问:pengwz] 如何改善锁相环的捕捉时间。 
[答:Shawn Han] 增大环路带宽  [2007-11-29 10:54:49]
[问:smilings] 请问小数分频能否实现N=1.023? 
[答:Noel Fung] That"s depends on the resolution of the PLL. For example, for a 12-bit fractional-N, the resolution is 1/2^12  [2007-11-29 10:55:13]
[问:ygz8827] 本机振荡器的特性和设计要素 
[答:Robert Shen] 1。频率范围。 2。响应速度。 3。稳定度。 4。噪声指标  [2007-11-29 10:55:39]
[问:sundong] 国半本振的最主要特点是什么? 
[答:Shawn Han] 低功耗,低相噪  [2007-11-29 10:57:06]
[问:whappin] 刚才您讲到:相位噪声与载波频率和偏置相关.这种相关是成比例的吗?如何进一步理解这种相关关系呢?谢谢 
[答:Robert Shen] 可参见PLL的设计专著http://www.national.com/appinfo/wireless/pll_designbook.html  [2007-11-29 10:57:33]
[问:hnldxhlfch] 可调频U段的无线话筒有不少谐振频点是什么原因? 
[答:Noel Fung] They have to operate at different channel or otherwise they will jam each other  [2007-11-29 10:57:42]
[问:kuersike] 本机振荡器的最优性能是什么? 
[答:Janet Wu] 在设计时,需综合考虑多个参数:相位噪声,锁定时间,相位余量。您可以通过仿真获得最优参数。 国半网站上有在线仿真工具:http://www.national.com/appinfo/wireless/webench/  [2007-11-29 10:57:56]
[问:zorro2774] 你好 我想问一下这种本机振荡器设计会对其他性能造成影响吗?例如,设备的反应时间? 谢谢 
[答:Shawn Han] 可以设计到几十微秒内锁定,一般不会影响整个系统的反应时间  [2007-11-29 10:58:32]
[问:steven1998] 你好,请问它的频率调谐范围是多少? 
[答:Robert Shen] 不同的产品都有自己的范围,请参见产品指南:http://www.national.com/appinfo/wireless/files/PLLSelGuide.pdf  [2007-11-29 10:59:05]
[问:reachle] 请问现在模拟PLL电路还有广泛应用吗?和数字PLL相比有有什么优点呢? 
[答:Noel Fung] analog PLL is still the perfered method because it is simple and reliable, most important, there are a lot of choice in the market  [2007-11-29 10:59:07]
[问:diandianxin2007] 本机振荡器在实际生产中会带来那几方面的优势? 
[答:Janet Wu] 在相位噪声,锁定时间,相位余量等参数能实现最优化设计。  [2007-11-29 11:00:04]
[问:hushuyu] 震荡电路,有没有其他优于别人的特性 
[答:Janet Wu] 您具体指的什么方面?  [2007-11-29 11:00:22]
[问:mhjuan119] 本机振荡器还有哪些需要改进的地方 
[答:Robert Shen] 根据具体要求,对不同的指标进行平衡给出最佳的设计。  [2007-11-29 11:01:23]
[问:accura] for a wide loop bw,we can ruduce the p/n by a good ref,but with a narrow bw,how to compress the peak near the carrier,the peak is just the loop bw. 
[答:Noel Fung] this peaking can only be reduce if you have a good close-in phase noise VCO. It is because the phase noise of VCO is reduced outside the loop BW. Within the loop BW, it depends on the VCO  [2007-11-29 11:01:33]
[问:hushuyu] 有无专业培训 
[答:Betty Lee] You can access www.natonal.com/CHS to get the latest product and technical information, including online seminars, appNotes, white papers, etc..  Furthermore, our Analog University also provides many online training trainings in which you can expand your knowledge and understanding of analog electronic technology.  Please access http://www.national.com/AU/  [2007-11-29 11:01:47]
[问:damihuang] 能否介绍NS的超高速千兆ADC和其配套的时钟分配,运放,后端接口芯片的解决方案?特别是时钟芯片。 
[答:Shawn Han] 时钟推荐LMX2531  [2007-11-29 11:02:04]
[问:ytyang] please introduce which types of fractional-N PLL can you offer,sigma-delta or DAC-based? 
[答:Robert Shen] Please take the selection guide for you reference:http://www.national.com/appinfo/wireless/files/PLLSelGuide.pdf  [2007-11-29 11:03:17]
[问:ytyang] 请问要测试一个锁相环的锁定时间和Jitter,应该用什么方法。 
[答:Noel Fung] you can use modulation domain analyzer or spectrum analyse to measure lock time. To measure jitter, either measure the phase noise and calculate jitter by yourself or use specific noise analyzer.  [2007-11-29 11:03:28]
[问:accura] 请问冯先生能否多讲解点环路的优化与评估?比如phase margin,zero和pole如何对应到现实电路中? 
[答:Noel Fung] it will be a long story. I recommend the book which is availabe in wireless.national.com. The book detailed all the anlaysis.  [2007-11-29 11:04:26]
[问:tongange] 你们的产品线包括 VCO  VCO+PLL,单独的分频器有没有? 
[答:Robert Shen] 单独的分频器没有。  [2007-11-29 11:04:30]
[问:BB1234] 如何设计低相位噪声的压控振荡器? 
[答:Robert Shen] 我们没有单独的压控振荡器。  [2007-11-29 11:05:10]
[问:kw2007] 振荡器的抖动和那些因素有关? 
[答:Janet Wu] 在现实世界中,相位噪声散布在整个频谱中,生成相位误差,并生成抖动.  [2007-11-29 11:05:48]
[问:joe.li] 如果本震有两颗VCO 来调振,一般是通过什么方式来控制? 
[答:Noel Fung] most PLL use three wires uwire or SPI control. usually you can share the Data and Clk pin and use LE pin to select which VCO is going to be controlled.  [2007-11-29 11:06:14]
[问:lubobgrimm] NI的压空振荡器在100K上的频率飘逸一般能达到多少? 
[答:Shawn Han] 国半没有单独的VCO产品,目前推出的是高集成度PLL+VCO的产品LMX2531。 频率漂移更大程度上取决于参考时钟的频漂。  [2007-11-29 11:07:10]
[问:elegance9527] 请问冯先生设计PLL时使用全差分结构吗?怎么平衡它跟版图面积(尤其是环路滤波器的电容)的关系呢? 
[答:Noel Fung] I would say single-ended charge pump is still the main stream.  [2007-11-29 11:07:49]
[问:spirithello] 对于振荡器电路PCB板的设计的一些特殊要求,非常希望听到专家的建议。 
[答:Shawn Han] 对于2GHz以下的频率,可以使用普通的FR4板材  [2007-11-29 11:08:13]
[问:sszzjj] 本机振荡器都可应用于那些领域 
[答:Janet Wu] 一般用于发射与接收通道中的中频本振和射频本振,属于无线通信设施中的心脏电路。  [2007-11-29 11:09:56]
[问:accura] 我个人认为,对于PLL在频谱仪方面的应用,商业化集成器件似乎并不适合,我们都是通过自己设计PLL来满足高速的扫频性能,请问专家在频谱仪的应用上商业化器件是否确实存在不足之处? 
[答:Robert Shen] 主要是看响应时间,频率范围。要看VCO的特性。一体化的产品在频谱仪上有限制。  [2007-11-29 11:09:59]
[问:accura] 对于频谱仪所用本振,要求范围宽,相噪好,锁定速度快,请问这对于环路应如何设计才能满足要求? 
[答:Noel Fung] the architecture used in spectrum analyzer is a bit different from other applications. usually, there are several LO to cover the wide frequency range. When you change the frequency of the spectrum analyzer, you can hear some "switching" noise from the analyzer  [2007-11-29 11:10:15]
[问:weiliya] 一个电容二极管的体质有多大? 
[答:Robert Shen] 取决于哪家的产品。NS没有电容二极管。  [2007-11-29 11:10:57]
[问:lyn663013] 请介绍此振荡器的性价比优势 
[答:Janet Wu] 本机振荡器在无线通讯应用中基本属于必选器件,国半在本振电路设计上有着悠久的历史。  [2007-11-29 11:11:35]
[问:hardwhere] 振荡器或时钟的抖动如何度量和测量? 
[答:Janet Wu] Jitter是相位噪声在一定频带内的积分,可以使用带jitter测试的频谱分析仪测试,或者测得相位噪声后,手工估算积分。  [2007-11-29 11:12:14]
[问:ecnanjing_EBY7E] 本振源的稳定度对VCO的精度有何影响? 
[答:Shawn Han] 本振输出的频率准确度更大程度上取决于参考时钟,VCO本身就是受调谐电压控制的  [2007-11-29 11:12:36]
[问:accura] how to design the charge pump? 
[答:Noel Fung] Did you mean how to select the charge pump current? Usually, high charge pump current will reduce the normalized noise contribution of the PLL. In addition, high loop bandwidth is possible with high charge pump current. At last, high charge pump current is required in order to reduce charge pump leakage due to loop filter or VCO  [2007-11-29 11:12:53]
[问:zorro2774] 你好 我们知道锁相环用于将VCO锁定在所需的频率上,我想问一下这种设计会对频率的调节造成影响吗? 谢谢 
[答:Robert Shen] 通常PLL可以在它的频率范围内进行调节并锁定。范围以外不能调节。  [2007-11-29 11:14:05]
[问:zhangwq] 变容二极管最小封装是多少? 
[答:Robert Shen] 取决于厂家,NS没有变容二极管。  [2007-11-29 11:14:44]
[问:elegance9527] 还一个问题,就是我们在电路仿真的时候怎么看相位噪声的大小呢?用Cadence Spectre或hspice可以吗 
[答:Noel Fung] I am not familiar with Cadence or Hspice, in fact I don"t know how they can perform simulation. As I mentioned in the seminar, PLL is a close loop system, it can be analyzed with standard transfer function. So the simulation is in fact a transfer function simulation, no matter it is a PLL or other control loop system. This method, is by far as accurate as it is expected.  [2007-11-29 11:15:06]
[主持人:ChinaECNet] 各位观众,现在用户提问很踊跃,专家正在逐一回答。请耐心等待您问题的答案,同一问题请不要多次提交。  [2007-11-29 11:15:56]
[问:ytyang] 我们知道电荷泵的充放电电流会有不匹配的现象,会影响VCO的控制电压,这种现象有可能会使环路不稳定么。怎么降低这种状况。 
[答:Shawn Han] 是的,会不稳定以至失锁。应当将VCO受控电压设计在电荷泵可达到的范围内,尽量居中。  [2007-11-29 11:16:13]
[问:wuling] 请问NS采用什么技术保证PLL可以快速捕获相位? 
[答:Robert Shen] 快速捕获是靠环路滤波的相应特性,它与误差相对。一个好的PLL是整体设计。NS由简单方便的设计工具,大家可以试试:http://webench.national.com/appinfo/wireless/webench/index.cgi  [2007-11-29 11:17:48]
[问:wuling] 请问如何选择loop bandwidth filter?根据哪些参数? 
[答:Shawn Han] 根据鉴相频率,相位噪声,锁定时间要求,优化折衷。 可使用国半在线仿真软件计算http://www.national.com/appinfo/wireless/webench/  [2007-11-29 11:18:28]
[问:zstone512] 设计一vco锁定在945MHZ时,相位噪声会时好时坏,但锁定在其他频率则不会有此种情况出现.这是什么原因引起的? 
[答:Noel Fung] some possible reasons: (1) at 945MHz, the VCO is not stable, for example, 945MHz is the max free running freq of the VCO. (2)the load at 945MHz is not 50ohm (3) the varactor diode is not linear at some bias points, etc  [2007-11-29 11:19:05]
[问:zhangwq] 变容二极管管控电压定义到多少? 
[答:Janet Wu] 不同产地的电容二极管反向电压定义不同,具体要看型号。  [2007-11-29 11:19:43]
[问:wuling] 请问相位余量如何选择,过大或过小会造成什么后果? 
[答:Robert Shen] 要与系统要求一致。过小,系统会不稳定,过大系统的其他指标会变差,如相应和误差。  [2007-11-29 11:21:36]
[问:zhangwq] 如何处理VCO电压漂移(温度变化). 
[答:Janet Wu] 首先要保持VCO负载固定,例如可以在VCO后级加上一个缓冲的放大器。另外,VCO的VCC端用一个低噪声的LDO来作为supply,例如国半的LP5900。对整个系统来说,需要加上PLL进行控制。  [2007-11-29 11:22:07]
[问:kw2007] NS有那些产品具有分数PLL的产品? 
[答:Robert Shen] 具体可参见产品指南:http://www.national.com/appinfo/wireless/files/PLLSelGuide.pdf  [2007-11-29 11:22:17]
[问:sszzjj] 贵公司的在线培训网址是什么 
[答:Betty Lee] You can access following URL to download our online seminar  (http://www.national.com/onlineseminar ) Or you can participate at our online training courses organized by National"s Analog University.  URL is http://www.national.com/AU  [2007-11-29 11:23:06]
[问:zxh720217] 相位误差会存在,频率越高误差会越大,所以出于对相位误差的考虑,频率跟踪是不可以太高的,是吗? 
[答:Noel Fung] since phase error comes from integrated phase noise, as long as the phase noise is low within the specific bandwidth, you"ll get low phase error no matter what is the VCO freqeuncy.  [2007-11-29 11:23:08]
[问:hardwhere] 目前VCO的频率精度和抖动达到什么样的水平? 
[答:Robert Shen] NS没有独立的VCO产品,不能给出准确的答案。  [2007-11-29 11:23:42]
[问:dingxiubing] VCO的相位噪音和那些因素有关? 
[答:Janet Wu] 在现实世界中,相位噪声散布在整个频谱中,生成相位误差,并生成抖动.  [2007-11-29 11:24:20]
[问:ecnanjing_EBY7E] 设计PLL时频压特性S曲线的斜率多少比较适合? 
[答:Shawn Han] 根据是否跳频,频段范围,锁定时间,相位噪声折衷而定。  [2007-11-29 11:24:35]
[问:张载涵] 请问用什么方法测量振荡器在仿真时的抖动 
[答:Janet Wu] Jitter是相位噪声在一定频带内的积分,可以使用带jitter测试的频谱分析仪测试,或者测得相位噪声后,手工估算积分。  [2007-11-29 11:24:49]
[问:marlin33] 回路滤波器有时会处现不稳定和振荡,请问专家如何避免或明或解决? 
[答:Robert Shen] 不稳定主要是回路相位余量不足,适当调整余量即可。  [2007-11-29 11:25:38]
[问:smilings] 能否简单解释小数分频为什么振动性能不好?剩余调制就是产生杂波吗? 
[答:Noel Fung] I don"t understand what is 振动性能 but the selection of PLL is application specific. For example, if you application requires very fine frequency resolution adjustment, integer-N PLL is not possible because the phase detector frequency limited the step size.  [2007-11-29 11:25:48]
[问:张志民] 请问小数分频的振动性能怎么样 
[答:Noel Fung] I don"t understand what is 振动性能  [2007-11-29 11:26:34]
[问:youngwg] 请专家介绍以一下的LMK03002相位噪声和调谐特性.谢谢! 
[答:Shawn Han] LMK03002 as a Clock generator performance (10 Hz - 20 MHz) 200 fs RMS jitter,VCO frequency: 1566 to 1724 MHz, Kvtune :11 to 15 MHz/V. Pls refer http://www.national.com/pf/LM/LMK03002C.html  [2007-11-29 11:28:12]
[问:key433] VCO如何影响到锁相环输出信号的相位噪声? 
[答:Robert Shen] VCO的输出信号的噪声会经过环路参与计算,对回路影响很大。因此,VCO的品质对系统影响很大。  [2007-11-29 11:29:28]
[问:caoyanping] 小数分频是怎么使N变小的呢?比如说整数N=10.和N=10.5哪个N小呢? 
[答:Noel Fung] I think your question is why fractional-N PLL can achieve small N. It is becasue you can select a very high phase detector frequency, PDF. since PDF=fvco/N, N could be very small. In integer-N PLL, PDF = step size and limited the possible value of N  [2007-11-29 11:30:18]
[问:dwwzl] 测量振荡波形对探头输入阻抗有没有具体的要求? 
[答:Noel Fung] usually, in RF system, we use 50ohm. So you can connect the VCO output to a spectrum analyzer. If you use a probe to measure the VCO, the probe must be high impedance and low capacitance  [2007-11-29 11:31:24]
[问:zhz-141] 本机振荡器所匹配的晶振有没有特殊要求? 
[答:Robert Shen] 没有特殊要求。但晶振的品质,如温度特性,一致性,对系统也有影响。  [2007-11-29 11:31:43]
[问:sszzjj] 本机振荡器如何设计到几十微秒内锁定? 
[答:Noel Fung] generally speaking, wide loop bandwidth reduce lock time, lock time approx equals to 4/loop BW  [2007-11-29 11:32:42]
[问:youngwg] NS的时钟电路如LMK03002,和其它公司相比,在成本上和性能上有什么优势? 
[答:Shawn Han] 内置PLL,VCO相噪指标都有优势,另外国半主推低功耗器件  [2007-11-29 11:33:12]
[问:tongange] KVCO怎么测试? 
[答:Janet Wu] Kvco定义为频率的变化与Vtune的改变。当Vtune变化时,变容二极管的电容发生变化,因而改变VCO的频率,每个VCO的数据手册都应该提供这个参数。Vtune中的噪声将对VCO进行频率调制,因此高Kvco表示高噪声灵敏度。  [2007-11-29 11:33:20]
[问:zhz-141] 本机振荡器在振动较大的场合,如汽车,能保证长时间的运行吗? 
[答:Robert Shen] 抗震是机械指标,与PCB,焊接,及减震器的使用有关,与系统的电气设计无关。  [2007-11-29 11:34:58]
[问:caoyanping] 如果要求产生88-132MHz频率,参考频率为10MHz,以您的经验来说,若采用小数分频,N为多少比较合适呢? 
[答:Noel Fung] if phase noise is very important, I will select the highest phase detector frequency, PDF, that the PLL support. For example, if max PDF is 10MHz, then PDF = fvco/N, N = fvco/PDF, N = 8.8 to 13.2  [2007-11-29 11:35:21]
[问:lanmail2003] 相位噪声和相位误差有什么差别? 
[答:Robert Shen] 噪声是随机的,误差是相对的。  [2007-11-29 11:36:30]
[问:tongange] PPT能不能发送给我的邮箱。 
[答:Betty Lee] The presentation and the video file will be uploaded to following website by end of next week. www.national.com/CHS/appinfo/wireless Pls feel free to download it.  [2007-11-29 11:36:32]
[问:key433] 锁相环输出信号的相位噪声由几个部分组成? 
[答:Janet Wu] 相位噪声定义为在载波和一个单边带的偏置之间的标称功率差。表述为 xx dBc/Hz@ yy Hz 偏置。与载波频率和偏置 相关   [2007-11-29 11:36:41]
[问:张载涵] 请问此振荡器的设计对相关性能有影响吗 
[答:Janet Wu] 您具体指哪方面的性能?如果是设备的反应时间,可以设计到几十微秒内锁定,一般不会影响整个系统的反应时间。  [2007-11-29 11:37:52]
[问:wupengjie2008] 为了改善VCO的相位噪音,NS采用了那些措施或技术? 
[答:Noel Fung] the phase noise of VCO depends on the Q-factor of the resonant element and also the process of the silicon. National has very good silicon process as well as technique to incease the Q-facotr  [2007-11-29 11:38:15]
[问:hnxxzkx] 贵公司河南有办事处吗? 
[答:Betty Lee] We have distributors covering the whole China.  Pls get their contact from following website. www.national.com/CHS/contacts  [2007-11-29 11:38:24]
[问:张志民] 请问增大环路带宽能否改善锁相环的捕捉时间 
[答:Shawn Han] 是。另外可考虑使用高阶环路滤波器。  [2007-11-29 11:39:21]
[问:xxtaotao] 有相关技术资料下载吗? 
[答:Betty Lee] You can download the relevant technical and product information from following website: wireless.national.com/CHS  [2007-11-29 11:39:26]
[问:cyberxx] 如何避免干扰 
[答:Robert Shen] 干扰是不可避免的,通过PCB的设计,元件的选择,抗干扰的电路设计都会起到减少对干扰的影响。  [2007-11-29 11:40:30]
[问:lichcct] 加环路滤波后对VCO的性能和相位噪音有什么影响? 
[答:Janet Wu] 会引入噪声到锁相环。3阶环路滤波器可以更好地降低寄生杂散。  [2007-11-29 11:41:41]
[问:elegance9527] 如果要把本地振荡器的jitter调到几ps,或者小于1个ps,电荷泵的不匹配和VCO自身的相位噪声在设计中哪个影响更大?谢谢!我自己觉得是电荷泵的影响大 
[答:Noel Fung] charge pump current will affect the normalized phase noise contribution of PLL. The overall phase noise is the summation of all phase noise in the system. So both VCO and PLL noise are important. Since jitter depends on the integrated BW, if your BW is small, PLL noise (charge pump dependent) is imporant, if the BW is large, VCO noise may be more important.  [2007-11-29 11:41:57]
[问:wupengjie2008] NS的时钟电路,输出电平有那几种?那种电平具有较好的相位噪声和抖动特性? 
[答:Shawn Han] LMK系列产品可输出LVDS和LVPECL电平,LVPECL抖动性能更好一些  [2007-11-29 11:42:23]
[问:zhz-141] 本机振荡器温度特性如何? 
[答:Robert Shen] 要看整体指标,如晶振,VCO的温度特性都会对本机振荡器温度特性有影响。  [2007-11-29 11:42:28]
[问:tongange] 环路带宽设计大小一般要采用多大?和主频的关系。环路带宽加大,和减小的 对噪声和锁定时间等其他参数有什么好处和坏处。 
[答:Noel Fung] I recommend you review the seminar again  [2007-11-29 11:42:48]
[问:cyberxx] 误差体现在哪些方面 
[答:Janet Wu] 主要体现在相位误差,抖动等。  [2007-11-29 11:43:21]
[问:hnzhengshasha] 测量使用什么仪器 
[答:Janet Wu] 可以使用带jitter测试的频谱分析仪测试  [2007-11-29 11:43:48]
[问:gaowenhai2005] 对于温漂,设计过程中应注意哪些方面 
[答:Noel Fung] you should select temp compensated capacitors, for example, NP0 or C0G capacitors  [2007-11-29 11:44:15]
[问:niuniuniu2020] 性能怎么样? 
[答:Janet Wu] 请问您问的是什么性能?国半在本振电路的设计上有着悠久的历史。  [2007-11-29 11:45:12]
[问:qiaopeng] 若要使用一个频率范围为200MHz-800MHz的振荡器,请您推荐一款NS公司的芯片 
[答:Shawn Han] LMX2485E  [2007-11-29 11:45:40]
[问:lichcct] PLL频繁失锁是什么原因造成? 
[答:Noel Fung] either the VCO is not stable and drift a lot or the charge pump leakage is serious. In addition, the phase margin of the PLL may be too low  [2007-11-29 11:46:04]
[主持人:ChinaECNet] 由于时间关系,本次中电网“在线座谈”马上就要结束了。虽然各位听众(网友)已与美国国家半导体公司的专家讨论了许多问题,但是还有许多提问没有来得及进行交流。本次在线座谈结束后,中电网将请美国国家半导体公司的专家继续答复所有的来自各位听众(网友)的提问,然后整理上载到中电网网站上,以便大家查阅  [2007-11-29 11:47:05]
[问:lanmail2003] 快速锁定的PLL除了在环路带宽,CP电流参数上有要求,对选用整数分频还是小数分频的结构上有什么要求? 
[答:Noel Fung] it is not related to the type of PLL, as you mentioned, fast lock increase CP and loop BW during lock only  [2007-11-29 11:47:05]
[问:qhcsc] 请问选择一个好的鉴相器,应该考虑哪些因素? 
[答:Robert Shen] 鉴相器在输入范围内的特征实鉴别好的鉴相器的重要指标,精度很重要,引入的噪声越小越好。  [2007-11-29 11:47:40]
[问:zhengyingjun] 设计中最主要的要素是哪些 
[答:Robert Shen] 稳定,相应快,误差小。  [2007-11-29 11:48:29]
[问:qhcsc] 请问如何减小小数分频器必然产生的杂波 
[答:Noel Fung] latest fractional-N PLL usually support high order modulator, for example, National support 4th order sigma delta modulator to reduce fractional spurious. In addition, dithering can reduce sub-fractional spurious  [2007-11-29 11:49:01]
[问:lanmail2003] PLL锁定的精度是否主要由晶体产生的参考频率决定? 
[答:Shawn Han] VCO的电源温度影响也需考虑,但参考源的稳定度是最重要的。如果是小数分频,小数分频的精度也是决定性因素。  [2007-11-29 11:49:49]
[问:xudz] 衡量本机振荡器的技术指标是什么?,NS的产品能做到什么程度? 
[答:Janet Wu] 有很多指标,包括环路带宽、相位余量、锁定时间和寄生杂散。NS在本振电路设计方面有着悠久的历史。我们提供了在线设计工具http://www.national.com/appinfo/wireless/webench,可以对充电泵电流、N计数器值、相位检测器频率等设计参数进行多项选择,综合考虑,以达到相位噪声、锁定时间和杂散参数的要求。  [2007-11-29 11:50:11]
[问:kszhl_2007] 本机振荡器的频率控制方法有哪几种? 
[答:Noel Fung] I think analog is still the preferred method. That is, the architecture we discussed today. DDS has been talking for several years but it is still not popular in most of the applications  [2007-11-29 11:51:04]
[问:tongange] 相位误差你们采用什么仪器来测量的? 
[答:Noel Fung] we used a very expensive equipment called noise analyzer, E5xxx from Agilent.  [2007-11-29 11:52:22]
[问:zhangweiqing] 如果参考时钟发生变化,如何去校正这个变化? 
[答:Shawn Han] 要看变化程度。PLL本身不提供校正,需要外部设置电路  [2007-11-29 11:52:32]
[问:zhengyingjun] 如果采用贵公司方案,设计中能得到哪些技术支持? 
[答:Robert Shen] 在线我们有技术支持和设计工具,评估板,CODELOADER软件可供用户使用。在内地我们有北京,上海,深圳办事处有应用工程师的技术支持。  [2007-11-29 11:52:44]
[问:zhengfei] 振荡器的抖动在怎样的范围? 
[答:Janet Wu] 当说明抖动或相位误差时,非常重要的是同时指定载波频率和综合带宽,在NS的产品datasheet中,都表明了这个参数,例如LMK03000中就有抖动的范围,见我们的演讲文档第23页。   [2007-11-29 11:52:45]
[问:hnzhengshasha] 和同类产品相比,价格怎么样? 
[答:Shawn Han] 根据使用量  [2007-11-29 11:52:50]
[问:lyn663013] 请问此振荡器的误差可以避免吗 
[答:Noel Fung] Which 振荡器?  [2007-11-29 11:52:59]
[问:ecnanjing_EBY7E] 请教相位稳定度与群时延的关系? 
[答:Noel Fung] the highest the phase margin, the longer the lock time  [2007-11-29 11:53:43]
[问:hnxxzkx] 如何购买? 
[答:Robert Shen] 通过代理商。授权的代理商如下:http://www.national.com./CHS/contacts/Details/China_map.html  [2007-11-29 11:54:12]
[问:tongange] 有源运放射机的设计有什么注意点:比如 振荡。 
[答:Janet Wu] 请问您所说的“有源运放射机”是指运放还是其它电路?  [2007-11-29 11:54:32]
[问:elegance9527] 请问NS的LMK系列产品采用的是标准CMOS工艺吗 
[答:Noel Fung] we used BiCMOS  [2007-11-29 11:54:40]
[问:niuniuniu2020] Kvco能达到什么样的值 
[答:Shawn Han] LMX2531一般在几到二十几MHz/V  [2007-11-29 11:55:14]
[问:wxnhappy] 噪音大吗? 
[答:Noel Fung] Which device are you referring to?  [2007-11-29 11:55:43]
[问:tongange] 专家方便留个联系方式吗?有些具体的问题,一时半会想不起来 
[答:Andrew Chiu] Please feel free to submit your questions to www.national.com/CHS/support We have experts to handle all these technical enquiries.  [2007-11-29 11:56:59]
[问:wxnhappy] 环路带宽是怎么测试呀??? 
[答:Janet Wu] 请参见我们的演讲文档第18页。  [2007-11-29 11:57:07]
[问:lanmail2003] 小数分频的结构中,PFD的频率设定为几十M,意味着晶体分出的参考频率也为几十M,但是高过20M的晶体在应用中不实际,请问这个问题是如何解决的? 
[答:Shawn Han] PDF设为等于或N分之参考晶振频率  [2007-11-29 11:58:17]
[问:ytyang] 能否详细解释下使用频谱分析仪测试锁定时间的方法 
[答:Janet Wu] 可以使用调制域分析仪或者频谱分析仪来测试。从演讲中可以知道,锁定时间和环路带宽的关系为锁定时间=4 / 环路带宽.  [2007-11-29 12:00:10]
[问:tongange] 你们是采用CMOS工艺的?还是别的工艺?高温的时候怎么考虑的?带隙电压采用那种方式?可以达到多大的精度(MV)? 
[答:Robert Shen] 不同的产品不用到不同的工艺,象LMX2531使用BICMOS8的工艺。具体的参数可以看具体的产品手册。  [2007-11-29 12:01:01]
[问:zxh720217] 如果我想实现几百k频率的零相位跟踪锁定,有什么比较先进的方案呢? 
[答:Shawn Han] 可以详细讨论一下  [2007-11-29 12:01:34]
[问:xxtaotao] 设计中对环境要求如何? 
[答:Robert Shen] 通常是室温环境。  [2007-11-29 12:01:35]
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