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| 主题：介绍NXP PCIe 器件 | ||
| 在线问答： | ||
| [主持人：ChinaECNet] | 各位听众（网友），上午好！欢迎参加中电网在线座谈。今天，我们有幸邀请到NXP公司的专家就“ 介绍NXP PCIe 器件”举行在线座谈。在座谈中，您可就您关心的问题与NXP公司的专家在线进行直接、实时的对话交流。中电网衷心希望通过大家的共同努力，不仅能够增进各位听众（网友）对“介绍NXP PCIe 器件”的了解和掌握，而且能够为大家事业的发展带来裨益。 | [2006-8-10 10:25:08] |
| [问：itc008] | 请问PCI-E的速度跟AGP4速的速度量化对比关系？哪个快？ | |
| [答：Lam] | AGP4 is supposed to be replaced by PCI Express. Actually, in new Intel-based motherboards, graphics cards are predominately offered by PCI Express instead of AGP already. PCI Express x16 is typically used for graphics, and the speed is 16 times 2.5Gb/s = 40Gb/s. | [2006-8-10 10:31:02] |
| [主持人：ChinaECNet] | 我们已经进入问答阶段如果听众想重温演讲或内容可以点击下面“回顾演示”重看演讲。 | [2006-8-10 10:31:55] |
| [问：lawyer] | PCI，PCI-X，PCI-Express这几种接口在性能和使用上有何区别或联系? | |
| [答：Lam] | PCI is parallel 33MHz/66MHz 32-bit/64-bit interface. PCI-X is an extended version of PCI, and is still a parallel interface with improved features. PCI Express is serial running at 2.5Gb/s for one lane, and is scalable to up to 16 lanes. So PCI Express is much higher speed, and uses only 4 serial lines for 2.5Gb/s! That is it is also easier for PCB layout and cheaper for total system cost. PCI Express is expected to replace PCI, PCI-X, AGP, PCMCIA PC Card, Cardbus etc. | [2006-8-10 10:34:41] |
| [问：qizhi_liu] | NXP PCIe现在有几款?参考价格多少？在中国市场是否已经有售？开发和使用这些芯片是否需要单独的开发环境，如驱动需要编写等？谢！ | |
| [答：RChen] | 目前NXP已供货的有X1 PHY 芯片PX1011A和通道开关CBTU0808,在中国市场已经有售,PX1011A少量的参考价是8美元,具体价格可以通过我们的代理AVNET询价.开发和使用这些芯片只需要一个FGPA开发环境.(XILINX...) | [2006-8-10 10:34:59] |
| [问：zhouwuqiang] | PCI E相比PCI的除速度外，最大特点是什么？ | |
| [答：Lam] | Please see our answer to a previous question. | [2006-8-10 10:36:25] |
| [主持人：ChinaECNet] | 在此回答问题的专家是NXP公司的：Ho Wai Wong-Lam、Aika Tsai、Richard Yu、Eric Wu、Richard Chen和 Christian Paquet。 | [2006-8-10 10:36:26] |
| [问：lawyer] | NXP是否提供PCIe的IP核? | |
| [答：RYu] | No, we don"t provide IP cores. We hv 3rd party partners providing IP cores. | [2006-8-10 10:36:44] |
| [问：elmer] | 能应用在哪些家电上? | |
| [答：Lam] | PCI Express is mainly used computer-based systems, but already some set-top boxes are using PCI Express as well. | [2006-8-10 10:37:34] |
| [问：spcatv] | PCI Express在数字电视机上有什么应用吗? | |
| [答：Lam] | To provide high-speed interface allowing multiple TV channels to be watched, recorded and processed simultaneously. | [2006-8-10 10:38:28] |
| [问：bobodu] | PCI Express和高速总线Hyper Transport 在性能上和应用上有何差别? | |
| [答：Lam] | PCI Express and HyperTransport are functionally similar. HyperTransport is mainly used for chip-chip interconnect on AMD platform. PCI Express is used for IO connectivity on both Intel and AMD based platforms. | [2006-8-10 10:40:32] |
| [问：ihopecao] | 您好，请问一下NXP又没有PCie toPCI的器件呢？ | |
| [答：Lam] | No. | [2006-8-10 10:40:43] |
| [问：qizhi_liu] | 请问：PCIE与PCI的软件兼容是代码级的还是源程序级的，需要重新编译或者修改代码吗？ | |
| [答：Christian] | In theary, the source code is indeed compatible with PCI. However, the PCIe code may have specific configuration registers. In that case, recompile is required | [2006-8-10 10:44:39] |
| [主持人：ChinaECNet] | 在此回答问题的专家是NXP公司的：Ho Wai Wong-Lam、Aika Tsai、Richard Yu、Eric Wu、Richard Chen和 Christian Paquet。 | [2006-8-10 10:47:00] |
| [主持人：ChinaECNet] | 各位观众，现在用户提问很踊跃，专家正在逐一回答。请耐心等待您问题的答案，同一问题请不要多次提交。 | [2006-8-10 10:51:35] |
| [问：飞翔青鸟] | PCI-Express在主从设备中使用时,如何做到时钟的同步? | |
| [答：Lam] | PCI Express does not require the transmitter and receiver to have the same clock. The clock is embedded in the data stream, and is recovered at the receiver side automatically. | [2006-8-10 10:51:51] |
| [主持人：ChinaECNet] | 各位观众，现在用户提问很踊跃，专家正在逐一回答。请耐心等待您问题的答案，同一问题请不要多次提交。 | [2006-8-10 10:53:43] |
| [问：qmyi] | 请问NXP PCIe的兼容性如何？ | |
| [答：Lam] | Very good. NXP PCI Express PHY solution is very well tested in a multitude of PC systems and many system-level tests have been done by NXP and our partners. So this is a very mature design and product. Many interoperability tests have been done. Please visit http://www.standardics.NXP.com/support /faq/interface/pcie.compliance/ | [2006-8-10 10:58:12] |
| [问：aquarius_song] | 请问NXP的PHY芯片和Ti的相比有什么优势？谢谢 | |
| [答：Lam] | NXP has a smaller package and lower power dissipation, which makes it ideal for all kinds of form factor, including ExpressCard modules. NXP PCI Express PHY solution is very well tested in a multitude of PC systems and many system-level tests have been done by NXP and our partners. So this is a very mature design and product. We work with many PCI Express IP vendors, so you have a wide choice of PCI Express IP vendors. There are also many 3rd party design kits with NXP PHY, so that you can test out your design without investing in your own PCB design. Many interoperability tests have been done. Please visit http://www.standardics.NXP.com/support /faq/interface/pcie.compliance/ | [2006-8-10 10:59:37] |
| [问：bobodu] | 串行PCI Express, 对时钟有何特别的要求如抖动和相位? | |
| [答：Lam] | PCI Express does not require the transmitter and receiver to have the same clock. The clock is embedded in the data stream, and is recovered at the receiver side automatically. | [2006-8-10 10:59:49] |
| [问：spcatv] | 如何确保PCI Express总线传输数据的安全性? | |
| [答：RChen] | NXP可以提供相关的技术文档,如PCB LAYOUT的技术文档来指导工程师,以提高PCI Express总线传输数据的安全性和可靠性 | [2006-8-10 11:00:48] |
| [问：飞翔青鸟] | ISA接口的延时很难控制,PCI中的延迟是否也很难控制? | |
| [答：RChen] | PCI-E是采用差分信号传输,很好的解决了传输过程中的延迟和同步问题 | [2006-8-10 11:03:14] |
| [问：kingq] | 用ASIC和FPGA来实现x1 PCI Express PHY有什么不同? | |
| [答：Lam] | The PCI Express digital protocol IP core has to reside on an FPGA or an ASIC. So either way, validation needs to be done to make sure that interoperability with PCI Express PHY is achieved. The difference between ASIC and FPGA is that FPGA is programmable, so you can change the digital code quickly. With ASIC, the RTL code is fixed in the ASIC. | [2006-8-10 11:03:32] |
| [问：spcatv] | PCIE是差分串行线，可以在铜缆或光钎上传播吗？ | |
| [答：RYu] | PCIe has differential input. Can it be used for copper cable or fiber optic? | [2006-8-10 11:04:00] |
| [问：qhfqc] | 目前PCI Express总线的数据传输速率能达到所高?最高速率下的传输距离有多远? | |
| [答：Christian] | The speed of PCI Express V1.0A and V1.1 is 2.5GHz for each lane. Of course the bandwidth is directly proportional to the nr of lanes (X1: 2.5Gb/s; x4:10Gb/s; etc..) The next generation of PCi Express, namely PCI 2.0 will double the speed: 5GHz. According to the spec, the max distance for PCI Express is 17inches on a PCB(FR4 material). | [2006-8-10 11:05:51] |
| [问：skyli] | 在台式计算机中,PCI独霸天下,PCI-Express能有多大的市场和前景? | |
| [答：RYu] | On new motherboard (no matter the chipset is 775, 965, 945, etc), there are now slots for PCI, PCIe (1, 4, 16). Most new peripheral cards are now available in PCIe. So PCI is being replaced by PCIe. | [2006-8-10 11:06:18] |
| [问：香辣小龙虾] | 请详细介绍PX1011A 和PX1012A有什么区别? | |
| [答：Lam] | The PX1012A is exclusively for customers who use PLDA IP Core. The PLDA PCI Express PXPIPE EZ IP Core is exclusively licensed for use with the NXP PX1012A. The PX1011A and PX1012A are pin-for-pin compatible and have the same functionality and transmit/receive performance. The NXP PX1012A and PLDA IP Core have passed extensive, proprietary system testing beyond PCI-SIG compliance tests. PX1011A is for customers who use other PCI Express cores, i.e. non-PLDA. | [2006-8-10 11:06:34] |
| [问：wgu] | x1 PCI Express PHY和x32 PCI Express PHY的传输速率有何不同? | |
| [答：RChen] | PCI-E每1个链路的名义传输速率为5G,所以x32 PCI Express PHY的传输速率为160.实际传输速率可能比名义传输速率低些,x1 PCI Express PHY为4,x32 PCI Express PHY的传输速率为128 | [2006-8-10 11:08:36] |
| [问：小宝MM] | 请问产品目前有没有量产？ | |
| [答：Lam] | Yes. Both commercial grade (0-70C) and (-40 to 85C) grade PX1011A / 1012A are in production. CBTU0808 is also in production. | [2006-8-10 11:10:23] |
| [问：海阔天空] | PCI-E会不会与AGP存在对显卡兼容问题？ | |
| [答：Lam] | PCIe and AGP cannot interoperate. | [2006-8-10 11:10:39] |
| [问：aquarius_song] | NXP有没有PCI转PCI-E的桥芯片？ | |
| [答：Lam] | No. | [2006-8-10 11:11:00] |
| [问：wgu] | PCI Express总线接口对降低电磁干扰(EMI)有何优势？ | |
| [答：Christian] | The advantage of PCI Express in terms of EMI is significant: instead of 32 bits toggling rail to rail as it is in PCI, you have only 2 x 2 differential signal toggling at max 1.2V. So the emission is much lower. | [2006-8-10 11:11:12] |
| [问：ceci] | 在DVD视频流媒体中,采用PCI Express PHY有什么好处,是降低成本还是提高质量? | |
| [答：RChen] | 在DVD视频流媒体中,采用PCI Express PHY,将提供足够大的带宽来传输视频流媒，提高传输质量，如果你的应用需要大的带宽，PCI Express PHY方案也是一个低成本的方案．另外PCI Express 将是未来的一个趋势，采用PCI Express 将会使你的设备有更好的扩展性 | [2006-8-10 11:12:36] |
| [问：hjldragon] | 目前NXP的PCI Express PHY通路开关最多有几路? | |
| [答：RChen] | 目前NXP的PCI Express 通路开关有２路通路开关，ＣＢＴＵ０８０８ | [2006-8-10 11:13:37] |
| [问：香辣小龙虾] | NXP PCI Express PHY解决方案,和FPGA 或ASIC与PCI Express IP相比,有什么优点 | |
| [答：RYu] | Our PCIe PHY chip is used together with FPGA. And you need to have IP in the FPGA so the FPGA/PCIe PHY chip can communicate with each other. So all these 3 things actually compliment each other. | [2006-8-10 11:14:46] |
| [问：chunyan630] | 你们提供样片吗，价格怎么样 | |
| [答：Lam] | Yes. We provide initial samples. Please contact our local sales person or our distributors for samples. You may also buy samples on the internet from our distributors in North America, if you want (e.g. Digikey, Avnet, Arrow and Future). The low-volume pricing varies from distributor to distributor. Please check on their websites. | [2006-8-10 11:14:51] |
| [问：skyli] | 目前PCI Express的传输路数最高可达多少路?总带宽呢? | |
| [答：Christian] | The speed is 2.5GHz/lane as specified by spec. V1.0A and V1.1. But the bandwidth directly depends upon the nr of lanes: X1: 2.5Gb/s x4: 10Gb/s x16: 40Gb/s x32: 80Gb/s (This is the max but nobody uses X32) So, today, the max speed - or bandwidth - is achieved with X16 (40Gbits/sec) | [2006-8-10 11:15:17] |
| [问：elmer] | 在高档微波炉上是否有应用? | |
| [答：RChen] | 是否有应用要看产品具体的技术要求，如果你需要大的数据传输速率，同时也让自己的产品具有更好的可扩展性，ＰＣＩ－Ｅ是一个较好的方案 | [2006-8-10 11:15:28] |
| [问：lewuming] | 为什么PCI Express架构特别适合图像传输? | |
| [答：Lam] | Mainly because of the high bandwidth... Frame grabbers are image processing computer boards that capture, process and store image data for a wide range of scientific, medical and industrial applications. Advances in image-sensing technology continue to put a greater demand on the interconnect bandwidth, as the number of pixels, frame rate and the number of cameras served by a single frame grabber all tend to increase. Some applications already would require throughput exceeding 1GB(ytes)/s!Many existing frame grabbers interface with the computer for further processing via the PCI bus, which allows real-time streaming of image data into system memory to make use of the increasing processing power of the host CPUs. While 32-bit 33MHz PCI can theoretically deliver 125MB/s, and 64-bit 33MHz PCI 250MB/s, the actual sustained performance is lower because of shared bus bandwidth and protocol overhead. The ever-demanding throughput requirement by frame grabber applications clearly goes beyond what is achievable in PCI technologies. PCI Express is meant to replace PCI and PCI-X in computers as the next-generation interconnect technology, which provides scalable bandwidth from x1 PCI Express of 250MB/s to x32 PCI Express of 8GB/s. Besides offering a much increased throughput, PCI Express also comes with a much smaller connector than PCI/PCI-X which lowers costs and eases PCB routing. To ease technology transition, PCI Express is backward compatible with PCI as far as software is concerned. With the ubiquitous adoption of PCI Express as the IO interconnect of choice in new computers, PCI Express technology offers a natural solution to solve the high throughput requirements of next-generation frame grabber applications. | [2006-8-10 11:16:08] |
| [问：海阔天空] | 请问PCI-Express的显卡能支持多显卡吗? | |
| [答：RChen] | 可以 | [2006-8-10 11:17:21] |
| [问：lewuming] | PCI Express在移动设备中有市场吗? | |
| [答：RYu] | It depends on what bandwidth you look for. We hv customers looking for PCI because they want to develop 3G equipment which requires higher bandwidth. | [2006-8-10 11:17:31] |
| [问：AlenPun] | PCI Express采用分层分包协议,包含3个协议层,请介绍每个协议层的用途.谢谢! | |
| [答：Lam] | This stack looks more similar to networking protocol like Ethernet than PCI. The software layer is where the application resides. The transaction layer translates PCI transaction requests from the software layer into packets. An important function of the transaction layer is flow control. The data link layer ensures data integrity during packet transmission and reception, and makes the unreliable link appear perfect to higher layers by retransmitting packets with errors. The physical layer’s main function is to get packets of data across the mechanical link, which may include PCB trace, connector, or cable, with a low bit error rate. | [2006-8-10 11:19:01] |
| [问：wupan34063] | 1x PCI-E的带宽是250MBps,4x和16x PCI-E的带宽是否4倍和16倍? | |
| [答：RYu] | Pls see the answer to a similar question below. PCIe x1 is at 2.5Gb/s. x4 and x16 stands for 4 lanes and 16 lanes respectively and so they are 4 times and 16 times of a 1x PCIe. | [2006-8-10 11:19:14] |
| [问：雨] | 为什么PCI Express不用并行接口而要采用串行接口? | |
| [答：Christian] | Serial IO has multiples advantages over parallel: Parallel can not go high speed because of: 1.Skew between individual bits of bus and clocks has to be very well controlled => make difficult the board layout 2. Bandwidth of bus has to be shared 3. Bandwidth per pin limited, not scalable Serial I/O has improved performance - Increased bandwidth per pin - No shared bus bandwidth limitations - Reduced noise and EMI - Easier board layout | [2006-8-10 11:19:47] |
| [主持人：ChinaECNet] | 各位观众，现在用户提问很踊跃，专家正在逐一回答。请耐心等待您问题的答案，同一问题请不要多次提交。 | [2006-8-10 11:22:02] |
| [问：wonliebuaa] | PCI Express PHY通路开关的带宽和动态范围有多大? | |
| [答：Christian] | The bandwidth of the PCIe PHY chip is 2.5Gbs for transmit and 2.5Gb/s for receive, in total 5Gb/s I am not sure as to what dynamic range refers to but if this refers to the minimim voltage range of the incoming signal, then it satisfies the specification, which is min .175V, max 1.2V. Pls let us know is the question is not well understood. | [2006-8-10 11:26:04] |
| [问：hedaizhu] | 串行总线和并行总线架构的主要差别是什么? | |
| [答：Lam] | Parallel buses run into high speed limitations because of skew between data and clock lines. On the parallel buses the bandwidth of bus has to be shared by all devices on the bus, and the bandwidth per pin is limited, not scalable. Why do we want to use serial I/O instead of parallel I/O? For parallel I/O, the skew between individual bits of bus and clocks has to be very well controlled, which increase the difficulty on PCB layout. In serial I/O, since the clock is embedded inside the data, there is no skew to control for x1 lane. Also, for serial point-to-point interconnect, devices don’t have to share bandwidth with other devices. You can reduce noise , which is a big help in any serial I/O system. Board layout is also made simpler with serial IO. | [2006-8-10 11:26:13] |
| [问：飞翔青鸟] | PCI Express的系统架构有什么特点? | |
| [答：Lam] | PCI Express is the next-generation of I/O interface replacing PCI. It uses serial point-to-point, dual simplex interconnect. Its speed is 2.5Gb/s per lane per direction. The differential signaling and low pin count, only 4 pins per lane, enable low cost implementations. PCI Express is software compatible with PCI. A PCI Express system will boot an existing OS with no changes to current drivers and application programs. PCI Express bandwidth is scalable from x1 at 2.5Gb/s up to x32 at 80Gb/s. For example, a x4 link will have 4 differential pairs and 10Gb/s bandwidth. PCI Express is a full duplex I/O interconnect, which means the transmitter and receiver can work simultaneously. With one lane, the speed is 2.5G bits/sec to transmit and 2.5Gbits/sec to receive giving you the raw bandwidth of 5Gbits/sec. With the overhead of 8b/10b encoding , the actual throughput is 4Gbits/sec. PCI Express uses 8b/10b coding. The purpose is to create sufficient 0-to-1, and 1-to-0 transition density in the bit stream for clock recovery at the receiver side. PCI Express performance is also highly scalable. This is achieved by implementing scalable numbers for lanes per interconnect based on requirement. | [2006-8-10 11:29:04] |
| [问：hedaizhu] | 和PCI/PCI-X相比,PCI –Express总线的特性是什么? | |
| [答：Lam] | Please see our answer for a previous question. | [2006-8-10 11:29:39] |
| [问：frzhang] | PCI Express能用在那些地方?和PCI相比,PCI-E支持那些新的使用模式? | |
| [答：Lam] | Wherever you find PCI, you will find PCI Express as well. So PCI Express is used on PC motherboards, add-on cards, and embedded systems, e.g. test equipment, medical equipment. Add-on card examples are graphics, audio / video cards, image grabbers, VoIP and telephone add-on cards etc. | [2006-8-10 11:32:15] |
| [问：zhangjs1] | 现在PCI EXPRESS 与PC主机PCI转接? | |
| [答：Lam] | Many new PC already provides PCI Express slots, and use PCI Express for chip-chip interconnect. | [2006-8-10 11:37:10] |
| [问：hjldragon] | 请介绍PCI Express PHY通路开关的串扰和信号失真问题? | |
| [答：RChen] | NXP的通道开关具有很好抗干扰性和信号失真, 并通过相关的行业测试,关于具体的指标数据,我们会在接下更新公布,请关注我们的相关产品更新信息. | [2006-8-10 11:37:45] |
| [问：cwg112112] | x1,x4,x8 和x16模式的PCI Express有些什么差别? | |
| [答：RChen] | 主要是带宽的区别,PCI-E 1个链路的带宽是5G,所以 X1是:5G, X1是:5G,X4是:20G,X8是:40G,X16是:80G,客户根据具体应用需要的带宽来选择多少个链路. | [2006-8-10 11:38:12] |
| [问：qhfqc] | PCI Express的系统架构和PCI相比,有什么改进和优点? | |
| [答：Lam] | In the parallel 32-bit PCI system, there are more than 32 wires, maybe even more than 64 to connect a PCI device to the host bridge. In the serial PCI Express system, there could be just 4 wires per endpoint. Also, bandwidth is 2.5Gb/s for PCI Express one-lane and is scalable to 2-lane, 4-lane... 16-lane. PCI bandwidth is much lower at 1Gb/s for 33MHz / 32-bit version. | [2006-8-10 11:42:00] |
| [问：bobodu] | PCI-Express 是串行的，PCI是并行的，PCI-Express的速度能比PCI快多少? | |
| [答：Christian] | PCI speed is limited. max speed is 132Mhz so the max bandwidth is 66x32 = 2Gb/s. However, this is not very common. Most of PCI busses operate at 33Mhz (bandwidth = 1Gb/s) Thanks to the scalability, PCI Express can reach bandwidth up to 80Gb/s: X1--> 2.5Gb/s x 2 (TX and RX) X2--> 5.0Gb/s x 2 x4--> 10Gb/s x 2 X16--> 40Gb/s X 2 X32--> 80Gb/s x 2 (X32 is not used yet however) | [2006-8-10 11:42:17] |
| [问：雨] | 和PCI总线相比, PCI Express接口的主要优点是什么? | |
| [答：Lam] | In the parallel PCI system, there are more than 32 wires, maybe even more than 64 to connect a PCI device to the host bridge. In the serial PCI Express system, there could be just 4 wires per endpoint. Also one-lane PCI Express is already 2.5Gb/s, versus 32-bit 33MHz PCI at 1Gb/s. PCI Express can scale to higher speed for 4-lane, 16-lane etc. | [2006-8-10 11:45:13] |
| [问：wantc] | PCI Express总线把并行改为串行, 速度是否会大幅度降低？ | |
| [答：Christian] | No, that is going to be the opposite. Serial will go much faster than parallel, for the following reasons: 1. Skew between individual bits of paralle bus and clocks has to be very well controlled => makes the board layout difficult. 2. Bandwidth of bus has to be shared 3. Bandwidth per pin limited, not scalable Serial I/O has improved performance 1. Increased bandwidth per pin 2. No shared bus bandwidth limitations 3. Reduced noise 4. Easier board layout For all those reasons, serial will be much faster than parallel | [2006-8-10 11:47:21] |
| [主持人：ChinaECNet] | 各位观众，现在用户提问很踊跃，专家正在逐一回答。请耐心等待您问题的答案，同一问题请不要多次提交。 | [2006-8-10 11:52:17] |
| [问：wupan34063] | 如何计算PCI-E的单向和双向传输带宽? | |
| [答：Christian] | The speed per lane is 2.5Ghz, this means that the bandwidth is 2.5Gb/s for the transmit and 2.5Gb/s for the receive, in total this is: 5Gb/s However, the real bandwidth is 80% of that number because there is 20% overhead in the PCI Express data stream due to 8b/10b encoding. So the real bandwidth is 2Gb/s one-way, 4Gb/s 2-way for a single lane PCIe. For multiple lane, simply multiply by the number of lanes. | [2006-8-10 11:52:19] |
| [问：TQM] | x16 PCI Express 总线是否要替代x8 AGP?是否要替代PCI/PCI-X? | |
| [答：Lam] | Yes - replacement of AGP and PCI and PCI-X in the long run. | [2006-8-10 11:57:39] |
| [问：cwg112112] | 16X PCI-E可以向下和8X4X2X1X PCI-E兼容吗？ | |
| [答：Christian] | The answer is believed to be yes. The PCIe specification details the downshift-ability for each lane. We know that X16 has to be downshiftable to X1 (mandatory) but X8, X4 and X2 may be optional or mandatory | [2006-8-10 12:01:09] |
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