Virtex-5 - 业界第一款65nm FPGA – 为何能提供更可靠的系统- 赛灵思厂商_在线座谈

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主题: Virtex-5 - 业界第一款65nm FPGA –为何能提供更可靠的系统
在线问答:
[主持人：ChinaECNet]	各位听众（网友），上午好！欢迎参加中电网在线座谈。今天，我们有幸邀请到Xilinx公司的专家就“ Virtex-5 - 业界第一款65nm FPGA –为何能提供更可靠的系统”举行在线座谈。在座谈中，您可就您关心的问题与Xilinx公司的专家在线进行直接、实时的对话交流。中电网衷心希望通过大家的共同努力，不仅能够增进各位听众（网友）对“Virtex-5 - 业界第一款65nm FPGA – 为何能提供更可靠的系统”的了解和掌握，而且能够为大家事业的发展带来裨益。	[2006-6-28 10:38:24]
[主持人：ChinaECNet]	我们已经进入问答阶段如果听众想重温演讲或内容可以点击下面“回顾演示”重看演讲。	[2006-6-28 10:47:18]
[问：michael.wxq]	请问你的这款芯片的主要优势表现在什么方面呀，你们的功耗做的如何？目前芯片功耗是个很重要的问题，也是芯片开发的瓶颈。
[答：Alfred]	Virtex-5 FPGA manufactures at 65nm process. The key advantages are:- 1) 20-30% lower in total power consumption compare to Virtex-4, which means that Virtex-5 is 50% lower in total power consumption compare to our nearest competitor offering. 2) Real 6-input LUT with diagonally symmetric interconnect pattern makes Virtex-5 35% higher in performance comparing to Virtex-4 3) Second generation of Sparse Chervon package technology reduces simultaneous switching noise 4) Build in PLL in every clock tile so that Virtex-5 will be able to generate precise phase clock with very low clock jitter 5) Etc…	[2006-6-28 10:48:51]
[问：hzp20001262]	该款FPGA主要应用与那些方面？
[答：Alfred]	By using 65nm process technology, Virtex-5 not only lowered the cost of FPGA, but it also able to achieve 35% higher performance and 20-30% lower in total power consumption. Additionally, Xilinx enhanced the DSP modules and embedded processing capability in Virtex-5. These make it suitable for a very wide range of applications including consumer products (Plasma TV, LCD TV), medical segments, telecommunication equipments etc..	[2006-6-28 10:50:15]
[问：real_pumpkin]	请问设计工具的支持怎么样？内部RAM的最高存储速度可以达到多少?
[答：Alfred]	Xilinx just announced ISE 8.2i. It supports Virtex-5 device. Block RAM can run at 550MHz.	[2006-6-28 10:51:59]
[问：yaobin@rd.china-putian.com]	现在消费类便携设备特别注重节能降耗设计，请问Virtex-5在这方面有什么独到体系结构和电源管理措施？谢谢！
[答：Alfred]	As for consumer applications, cost is a big concern. In order to lower down the cost, every silicon vendors tried to use the latest process technology to achieve that. However, the challenges is that when we use the smallest process technology, static power (leakage power) becomes half of total power consumption. Virtex-5 FPGA uses triple oxide technology to reduce static power, so that it is comparable to Virtex-4. Additionally, the core voltage of Virtex-5 reduces from 1.2V to 1V which lowered dynamic power by 35%.	[2006-6-28 10:55:48]
[问：kennypan]	what is the mass production schedule for V5? What are the key features of V5? what are the key advantages compared with Xinlinx competitors products?
[答：Alfred]	The mass production of V5 is Q4CY06, samples are available today. Virtex-5 FPGA manufactures at 65nm process. The key advantages are:- 1) 20-30% lower in total power consumption compare to Virtex-4, which means that Virtex-5 is 50% lower in total power consumption compare to our nearest competitor offering. 2) Real 6-input LUT with diagonally symmetric interconnect pattern makes Virtex-5 35% higher in performance comparing to Virtex-4 3) Second generation of Sparse Chervon package technology reduces simultaneous switching noise 4) Build in PLL in every clock tile so that Virtex-5 will be able to generate precise phase clock with very low clock jitter 5) Etc…	[2006-6-28 10:56:51]
[主持人：ChinaECNet]	在此回答问题的专家是Xilinx公司的：Alfred Chow、Liang Xiaoming和Sharon Lian。	[2006-6-28 10:57:14]
[问：jwfeng]	请问Virtex-5 的功耗最低可达到多少，是否适合于便携式低功耗仪表的使用，谢谢！
[答：XiaoMing]	Virtex-5在具体应用中的功耗与时钟频率、器件资源使用情况、晶体管翻转率、内存读写率等参数相关。考虑静态功耗的因素，同一系列中比较小的器件静态功耗较低。因此客户要控制器件的最低功耗，就需要在设计时充分考虑上述因素。客户可以用Virtex-5的功耗估算工具计算具体工作状况下的功耗值。由于具体指标范围跨度比较大，在此不便给出特定的最小值。在极限情况下，您可以将器件静态功耗看成极小值。根据以往的经验，有客户将Virtex-4 FPGA用于便携式的示波器，超声波设备等便携式仪表。Virtex-5比 Virtex-4 FPGA 功耗更低。建议您根据具体的应用，利用功耗估算工具进行功耗指标的具体评估。	[2006-6-28 10:57:18]
[问：zhumxa]	有没有Interconnect resource结构的相关资料呢？
[答：Alfred]	Virtex-5 interconnect is "diagonally symmetric", it reduces the number of hops required to connect one CLB to others, so that it"s able to reduce the interconenct delay, achieving 35% higher performance. The following is a URL pointing to a white paper which detail on how Virtex-5 achieve higher performance: http://www.xilinx.com/bvdocs/whitepapers/wp245.pdf	[2006-6-28 11:00:15]
[问：pearlshell]	V5使用了pll，是否说明pll比dcm更好？ V5降低功耗除了工艺方面的改进，还使用了什么方法进一步降低功耗？
[答：Alfred]	Xilinx included PLL in our Virtex-5 technology it becuase that PLL is good at controlling clock jitter. DLL is good at generating precise phase clocks. Thus, it serves two different purpose. As for the power consumption advantage we have had with Virtex-5, here is a few key reasons:- 1) Triple oxide technology 2) Circuit design technique to do tradeoff between speed and leakage power 3) Real 6-input architecture to integrate more logic into one CLB 4) Diagonally symmetric interconnect to reduce interconenct routing, so does the interconnect capacitance 5) XPower Estimator and Analyzer	[2006-6-28 11:05:37]
[问：kandyliuy]	V5和Quicklogic的一些低功耗fpga相比有什么优点？
[答：XiaoMing]	Virtex-5是高性能的可编程的系统平台，提供全面的系统级应用功能集合，以及同级别FPGA中非常优秀的功耗指标。在绝大多数场合，Quicklogic 的低功耗FPGA无法与Virtex-5形成直接竞争的关系。在极低功耗可编程器件方面，Xilinx 的CoolRunner II 系列器件是现在业界应用最广泛的低功耗可编程器件，广泛用于智能手机和其他电池供电设备。此外，Xilinx 的Spartan-3L器件广泛用于有待机功耗要求的消费类电子设备。	[2006-6-28 11:06:58]
[问：wypqq2qq]	请问Virtex-5的三极栅氧化层技术是否在新的spartan器件上使用？谢谢！
[答：Alfred]	We do not have a plan to use triple oxide technology in Spartan series yet.	[2006-6-28 11:10:29]
[问：zsz810924]	请问，利用virtex－5系列的fpga设计fifo，所能达到的最大读写速率是多少呀？
[答：Alfred]	550MHz X data bit	[2006-6-28 11:11:26]
[问：real_pumpkin]	I need to know the maximam speed of the internal ram block.
[答：XiaoMing]	1. 内部 Block RAM 最高可以运行在550MHz 时钟频率，Block RAM可以配置成多速率FIFO也可以运行在550MHz 时钟频率。	[2006-6-28 11:12:27]
[问：peng1yuan@hotmail.com]	现在virtes-5有没有比较好的应用案例或者方案？
[答：Alfred]	Please visit the following URL for details: http://www.xilinx-china.com/products /silicon_solutions/fpgas/virtex/virtex5/index.htm	[2006-6-28 11:13:58]
[主持人：ChinaECNet]	各位观众，现在用户提问很踊跃，专家正在逐一回答。请耐心等待您问题的答案，同一问题请不要多次提交。	[2006-6-28 11:14:42]
[问：real_pumpkin]	Can I use the internal ram as buffer for high speed DAC > 400MSPS?
[答：XiaoMing]	当然可以，Virtex-5的内部Block RAM 和配套的FIFO都可以运行在550Mhz时钟频率，完全满足您的要求。	[2006-6-28 11:16:45]
[问：大暑]	请问Virtex-5使用的6输入查找表在设计中会比4输入查找表节省资源吗?
[答：Alfred]	Yes, it will. Since you can integrate more logic into one Real 6-input CLB, so that you will be able to reduce the need to connect to other CLB. That means, you will be able to reduce the interconnect capacitance, so does the dynamic power consumption.	[2006-6-28 11:21:56]
[问：efly82]	影响Xpower估计器的精确度有那些因素?
[答：Alfred]	Xpower estimate power consumption base on .vcd file. vcd file is generated by simulation. Thus, your simulation pattern will very much determine how accurate is your XPower result.	[2006-6-28 11:23:49]
[问：tango]	请问产品的价格和altera的同类产品做比,哪个更好.
[答：Alfred]	Our competitor do not have 65nm FPGA yet. Thus, we can"t compare.	[2006-6-28 11:24:37]
[问：efly82]	如何来确定最坏情况下的功耗?
[答：Alfred]	It depends on your operating range. You should set the operating temperature to your maximium allowable temperature, since junction temperature affects leakage current a lot.	[2006-6-28 11:26:26]
[问：大暑]	请问他的DCM和以前的比较有什么改变吗?
[答：XiaoMing]	在时钟管理方面，Virtex-5入了CMT的概念，同时引入了PLL作为DCM的辅助。Virtex-5中第五代的全数字DCM配合新的PLL可以支持高达710 MHz的时钟管理。在时钟合成方面， PLL Synthesize Fout = Fin * M/(DO) M: 1-64, D: 1-52, O: 1-128 DCM Synthesize Fout = Fin M/D M, D values up to 32	[2006-6-28 11:26:37]
[主持人：ChinaECNet]	各位观众，现在用户提问很踊跃，专家正在逐一回答。请耐心等待您问题的答案，同一问题请不要多次提交。	[2006-6-28 11:26:52]
[主持人：ChinaECNet]	各位观众，现在用户提问很踊跃，专家正在逐一回答。请耐心等待您问题的答案，同一问题请不要多次提交。	[2006-6-28 11:28:29]
[问：xbao]	一般来说,漏电流随工艺尺寸的降低而增加,V5采用65nm深亚微米技术,有什么措施使V5的漏电流和V4相当?
[答：Alfred]	Triple oxide technology is the solution. Leakage current is affected by two factors:- 1) Oxide thickness - leakage fro gate to channel 2) Thershold voltage of a transistor - leakage from source to drain By using triple oxide technology, Xilinx carfully choose different oxide thickness for differect transistors, so that we are able to have different thershold voltage for different transistor as well. As a result, we are able to manage the leakage power to be comparable to Virtex-4	[2006-6-28 11:29:33]
[问：xq0515]	时钟会消耗许多功率,如何对时钟进行管理来降低功耗?
[答：XiaoMing]	功耗与晶体管翻转率成正比关系，在工作条件允许情况下，通过降低时钟频率或者暂时关闭时钟输入可以降低功耗。Virtex-5中有专用的时钟切换部件用于时钟切换，可以保证时钟切换时无毛刺。	[2006-6-28 11:30:01]
[问：shic]	我想问下目前XILINX的对手是哪几个品牌
[答：Alfred]	We are the only FPGA vendor offering 65nm FPGA today.	[2006-6-28 11:31:48]
[问：zsz810924]	我曾经用spartan3系列的3s1500自己设计的一个fifo他的最大读写速率只能达到30M左右，请问是不是需要编写很好的时间约束文件呀
[答：XiaoMing]	估计你的设计中没有加上速度约束。Xilinx的参考设计中3S1500的FIFO可以运行在166Mhz或更高。建议改善您的设计。	[2006-6-28 11:37:59]
[主持人：ChinaECNet]	各位观众，现在用户提问很踊跃，专家正在逐一回答。请耐心等待您问题的答案，同一问题请不要多次提交。	[2006-6-28 11:39:47]
[问：wangxg]	演示中说,100MHz时,V5中的XtremeDSP Slice比V4能降低功耗75%,能否说明功耗降低的原因?
[答：XiaoMing]	功耗降低主要来自： 1.XtremeDSP Slice结构的改善 2.Xilinx 应用Triple Oxide技术以及优化设计。 3.65nm工艺带来的动态功耗降低	[2006-6-28 11:41:11]
[问：huangby]	对FPGA来说,采用开关电源和LDO线性电源,那个会有优越性或更好?
[答：XiaoMing]	Virtex-5的Power Integrity 性能很好。只要达到FPGA对输入电源的技术指标要求，开关电源和LDO都可以用。特别指出，在为高速模拟电路供电的场合，例如MGT高速串行口供电部分，通常使用独立的LDO。	[2006-6-28 11:46:00]
[主持人：ChinaECNet]	所有问题均已提交给Xilinx公司的专家。座谈期间未回答的问题，Xilinx公司专家也会逐一回答，并在中电网上公布，请大家注意收看。	[2006-6-28 11:46:13]
[主持人：ChinaECNet]	由于时间关系，本次中电网“在线座谈”马上就要结束了。虽然各位听众（网友）已与Xilinx公司的专家讨论了许多问题，但是还有许多提问没有来得及进行交流。本次在线座谈结束后，中电网将请Xilinx公司的专家继续答复所有的来自各位听众（网友）的提问，然后整理上载到中电网网站上，以便大家查阅。	[2006-6-28 11:46:45]
[主持人：ChinaECNet]	在此，中电网特别感谢给予本次中电网在线座谈巨大支持的Xilinx公司，特别感谢专门在线回答各位听众（网友）提问的Xilinx公司的各位专家们，特别感谢各位听众（网友）积极热情的参与。祝大家事业有成、生活愉快！欢迎多提宝贵意见，欢迎关注中电网，下次再见。	[2006-6-28 11:47:03]
[问：wangxg]	V5中的功耗包括静态功耗,I/O动态功耗以及内核的动态功耗等几部分,请问专家,这几部分的功耗的分配如何?能给出大约的百分比吗?
[答：Alfred]	It various from one design to the other. As a rule of thumb, Virtex-5 static power is roughly 20-25% of dynamice power at the core. Without using triple oxide technology, we observed that our competitor 90nm FPGA"s static power is more or less the same as their dynamic power. Thus, you need to be very careful. As for I/O power, it"s purely depending on your I/O standard.	[2006-6-28 11:48:06]

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