如何利用增量设计流程缩短FPGA设计周期- 爱特公司厂商_在线座谈

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主题:如何利用增量设计流程缩短FPGA设计周期
在线问答:
[问：hdqiang]	Actel的FPGA可以实现MPEG4的编解码吗？
[答：Albert_Tai]	Yes, it can	[2004-9-29 10:25:01]
[问：liunavy]	请问门数和宏单元数有什么区别，怎么确定自己的设计需要多少门的芯片呀？菜鸟提问，多多包含！！
[答：Albert_Tai]	A macro may need many gate to implement, most IP (macro) will give out their gate count requirement	[2004-9-29 10:26:13]
[问：yuanjunsun]	您好：我来自武汉烽火通信，我想问的是不同的逻辑综合工具其各自的特点都有哪些，不同厂家的FPGA应对应于采用哪一种综合工具才能使综合出来的结果能最大限度的发挥该FPGA芯片的性能？谢谢！
[答：Albert_Tai]	Different synthesis products have differenet performance (speed) and outcome (gate count). Currently Synplicity"s Synplify Pro is known to be the best in these two areas	[2004-9-29 10:27:28]
[问：boyfly]	软件从哪个版本开始有“增量设计流程“得支持呀？
[答：Albert_Tai]	Synplify Pro. 7.5.1A	[2004-9-29 10:27:41]
[问：zoujilin]	Actel用来设计FPGA的软件是什么，对于增量设计是否可以很好的支持？
[答：Albert_Tai]	Libero is the development software for Actel"s FPGA, starting from version 6.0, Libero provides very good support for incremental design flow	[2004-9-29 10:28:56]
[问：zhfewq]	1、何设计工具？ 2、该设计工具通用性如何？（能否支持Xilinx公司的FPGA） 3、在该设计工具下，有无已经实用的“软处理器核”？
[答：Albert_Tai]	Libero development software only supports Actel"s FPGA. Actel also has a wide range of soft CPU IP that can be used on Libero	[2004-9-29 10:30:24]
[问：whyeah]	布局布线完成后，如何锁定布局和布线关系，从而保持设计中未修改部分的性能。
[答：Albert_Tai]	You can do this by choosing "incremental routing" and "incremental placement" options in Designer	[2004-9-29 10:31:20]
[问：cysheng]	在综合中设置总量设计的话，怎样保证能够在布局布线时将对应的逻辑锁定？是否需要在布局布线时指定约束？
[答：Albert_Tai]	Yes!	[2004-9-29 10:31:43]
[问：encaon]	一般来讲,采用增量设计,设计时间能缩短多少?
[答：Albert_Tai]	It all depends on how offen you modify your design.	[2004-9-29 10:32:22]
[问：liulinquan]	能否简单介绍一下ACTEL FPGA系列及其性能特点？
[答：Albert_Tai]	Flash family: Reprogrammable Secure Live at power-up Single chip Low power consumption Antifuse family: Scecure Live at power-up Single chip Low power consumption	[2004-9-29 10:33:39]
[问：hwyuyu]	请问在FPGA中采用异步逻辑需注意什么问题?我在进行逻辑设计时,经常出现逻辑在仿真时,逻辑关系非常正确,但下载到逻辑中,其逻辑总有一些小问题,但改变逻辑设计的顺序,便可以,这是为什么?是否瑜编译设置等有关?我不懂增量设计,能否说明增量设计的实际方法?谢谢!
[答：Albert_Tai]	For asynchronous design, you need to pay attention to the timing, especially the variatioin between best case and worse case. Detailed functional simulation is a must to guarantee to its functionality in all condition.	[2004-9-29 10:35:30]
[问：lzjtuwangzhe]	请问除了Synplicity公司的Synplify Actel支持增量设计以外，还有哪些综合工具支持增量设计呢？后端工具呢？谢谢！
[答：Albert_Tai]	Leonardo Spectrum from Mentor Graphics	[2004-9-29 10:36:21]
[问：hktk]	are there some differences between multi-ponit synthesis and incremental design flow?
[答：Albert_Tai]	Multi-point synthesis is just a part of incremental design flow	[2004-9-29 10:36:42]
[问：boyfly]	对actel的软件呢，libero5.0支持增量设计码
[答：Albert_Tai]	No, full incremental design flow support is available in Libero 6.0 and upward. Before 6.0, only the place and route software (Designer) support incremetal flow.	[2004-9-29 10:37:59]
[问：brotherjam]	增量综合的效果和重新综合，布线的效果相差大吗？
[答：Albert_Tai]	Incremental synthesis will try to keep the existing layout unchanged. While a full synthesis may produce a entirely different layout	[2004-9-29 10:39:07]
[问：chlfatso]	采用现代EDA设计工具所提供的增量设计流程,能有效地降低迭代设计所用的时间,是否是对设计流程的简化或步骤的融合,同时是否需要更大的硬件空间和更快的响应时间?
[答：Albert_Tai]	No, the benefit comes from its ability to ignore those repetitive steps	[2004-9-29 10:41:25]
[问：boyfly]	请问actel的apa芯片为什么同一型号芯片有的只能用串口编程，并口编不上，而有的用并口行，用串口不行呢？
[答：Albert_Tai]	The programming of APA is through it JTAG interface. Some third party vendor might provide serial interface programmer, but the data will eventaully converted in to serial JTAG bitstream	[2004-9-29 10:43:00]
[问：luogongqiang]	是否有好的FPGA的仿真系统可供参考?
[答：Albert_Tai]	ModelSim from Mentor Graphics	[2004-9-29 10:43:12]
[问：luogongqiang]	现在很多器件的工作电压都很低,FPGA设计低电压集成电路时应注意什么？
[答：Albert_Tai]	You need to pay attentions to the ground plan design. Poor ground plan will cause excessive ground bounce and affect the reliability of a low voltage design	[2004-9-29 10:44:34]
[问：fatfox]	在开发工具中如何观察使用资源的实现报告?
[答：Albert_Tai]	You can see the report in both the synthesis tool and place and route tool. The place and route tool provides the most accurate result	[2004-9-29 10:45:22]
[问：sfm7739]	ACTEL的FPGA一般设计可以达到的最高主频是多少？
[答：Albert_Tai]	The internal speed can reach 180MHz, while the I/O speed is around 150MHz	[2004-9-29 10:46:27]
[问：cyj622]	请问mpeg4级的设计需要应用什么级别以上的fpga芯片才够用
[答：Albert_Tai]	It depends on which functionality of mpeg4 you want to implement in fpga	[2004-9-29 10:47:36]
[问：boyfly]	其实使用actel的芯片时，发现每次布局布线后仿真结果相差很大，今天看来可以通过具体方法改善，actel可否针对这一部分写一份文档，我感觉作用很大的，因为fpga的延时不可测是大弊端，你刚才说的锁定哪个功能，好像可以改善很多呢
[答：Albert_Tai]	Yes, you"re right!	[2004-9-29 10:47:58]
[问：harry2004]	综合工具哪一种比较好
[答：Albert_Tai]	Personally I recommend Synplify Pro from Synplicity Leonardo Spectrum from Mentor Graphics is also pretty good.	[2004-9-29 10:48:40]
[问：solrr]	增量设计是否会产生冗余？如何控制冗余量？
[答：Albert_Tai]	Yes, but not much. It will only occur on the boundary of the block (compile point)	[2004-9-29 10:49:18]
[问：maeleton1]	对多通道多任务的信息，处理器的处理能力及相应的缓冲存储器是很重要的，Actel那些器件能胜任这一任务?它的能力如何？
[答：Albert_Tai]	APA (flash architecture) and Axcelerator (anti-fuse architecture) could meet your requirements	[2004-9-29 10:50:10]
[问：fatfox]	actel现在的工具可以进行功耗的分析吗?
[答：Albert_Tai]	Yes it can	[2004-9-29 10:50:24]
[问：encaon]	进行FPGA设计，经常需要向其它芯片提供时钟，这时将涉及提供时钟反馈的问题,有没有较好的方法？
[答：Albert_Tai]	You can use the on-chip PLL to solve this problem	[2004-9-29 10:50:57]
[问：brotherjam]	对增量总和，在布局布线时要用什么约束呢？
[答：Albert_Tai]	You only need to tell the place and route tool (Designer) to fix the existing placement and routing	[2004-9-29 10:51:28]
[问：fatfox]	actel的接口逻辑电压是多少?驱动能力怎么样?
[答：Albert_Tai]	It depends in the FPGA family. Some of them support 5V, 3.3V, 2.5V. Some even support 1.8V I/O standards. The I/O driving capability and depends on FPGA device, some can be as high as 24mA	[2004-9-29 10:53:50]
[问：brotherjam]	Are there any way to solve the clock skew in the fpga? not at the interface.
[答：Albert_Tai]	Yes, Actel FPGA provides several mean and resource on the chip to address the clock skew issue. For example, global clock, spine clock networks, PLL and special layout constraints.	[2004-9-29 10:55:11]
[问：luogongqiang]	那些设计软件和FPGA器件可支持增量设计?
[答：Albert_Tai]	Synplify Pro and Designer	[2004-9-29 10:55:26]
[问：xly6]	我以前一直使用ALTERA的CPLD/FPGA,请问你们公司的FPGA和我以前使用的ALTERA的在使用上差别大吗？如何能尽快的熟练你们的FPGA的开发流程？请推荐一款你们的配套软件！谢谢！
[答：Albert_Tai]	Actel"s FPGA is architecturally from Altera. Actel"s fine grain architecture has a lot of advantages over CPLD, you may contact one of our distributor in China to get a free deveopment software for your evaluation	[2004-9-29 10:57:06]
[问：maeleton1]	增量设计需要有什么设计准则?
[答：Albert_Tai]	There is no special rule in incremental design flow. The only suggestion is not make too much changes to a block each time	[2004-9-29 10:58:21]
[问：hdqiang]	请问在实现MPEG4编解码方面有实例吗？
[答：Albert_Tai]	We have some IP partners supplying similar cores right now, please visit our website for more information: www.actel.com	[2004-9-29 10:59:04]
[问：boyfly]	actel的芯片对不同电压的上电顺序要求严格吗？
[答：Albert_Tai]	Some FPGA do require special power-up sequence. For modern FPGA families, we do not have strict power-up sequence requirement. However, in some cases when the other components in a system is concerned, user might be suggested to follow the recommended power-up sequence.	[2004-9-29 11:02:00]
[问：rogerbenben]	Q1：请问此设计流程是否适合FPGA与FPAA结合的混合信号设计场合？
[答：Albert_Tai]	Yes	[2004-9-29 11:02:15]
[问：fatfox]	请问片上的pll倍频功能的上限是多少?
[答：Albert_Tai]	Different FPGA family has different frequency multplication factors. However, most of the time, the output frequency of a PLL becomes a limit instead of its multiplication factor. Normally 16x or 32x is not uncommon.	[2004-9-29 11:03:39]
[问：maeleton1]	Actel的那些器件可以替代ASIC功能?有何相应的设计软件?
[答：Albert_Tai]	APA family. Actel can provide the ASIC converstion service for our customers	[2004-9-29 11:04:21]
[问：hktk]	除了您所介绍的EDA工具外，还有哪些业界的工具也支持增量设计流程？
[答：Albert_Tai]	Leonardo Spectrum from Mentor Graphics	[2004-9-29 11:04:43]
[问：zzkeng]	FPGA中的时序设计如何进行验证?它的成功率大约有多少?和实测会有多大差别?
[答：Albert_Tai]	Timing simulation is the most basic timing verification approach, but it depends on the coverage of the testvector. Static timing analysis is another very powerful timing analysis tools, which can detect hidden and potential timing problems	[2004-9-29 11:06:08]
[问：zzkeng]	在进行FPGA设计时,如何避免时序的冲突问题?如何确定时序?
[答：Albert_Tai]	You may use simulation or static timing analysis tools to do this	[2004-9-29 11:07:05]
[问：zzkeng]	在设计过程中，如何使软件仿真最大限度地接近最终实际电路的工作情况？
[答：Albert_Tai]	Normally, if a design is full synchronous, its simulation result will match its actual behavior on the board.	[2004-9-29 11:08:12]
[问：xeron]	synplify pro7.7明确指出增量综合是面向altera和xilinx的，我采用actel ax500芯片,如何实现增量设计？
[答：Albert_Tai]	As mentioned in the presentation, only the Actel version of Synplify Pro supports incremental sysnthesis. It starts from Synplify Pro 7.5.1A Here the "A" referes to Actel version	[2004-9-29 11:09:31]
[问：zzkeng]	对于多时钟的系统设计,要注意什么问题?时序的排列和安排有什么要注意的规则?
[答：Albert_Tai]	You have to pay attentions to the total available global clock resource, and the intersection of multiclock domain	[2004-9-29 11:10:45]
[问：senlinchen]	增量设计具有很大的意义，我们的一个设计一次编译往往需要20-30分钟，但锁定那些已经布局过的异步电路（组合电路），可能能带到较好的局部模块的性能，但是否一定能得到最好的全局性能？
[答：Albert_Tai]	No, it may not produce an optimum result. But most of the time, we need to trade off between time and performance. The most important thing is to meet the target requirement in a resonable time.	[2004-9-29 11:12:53]
[问：boyfly]	actgen产生的fifo都是9位的，每个块为256x9，我的数据都是8位的，那么每个块能否工作为288x8，还是浪费每个word的一位呢？
[答：Albert_Tai]	Yes, you use 8 bits in a fifo, and the remaining one bit will be wasted.	[2004-9-29 11:14:08]
[问：dreamwalkers]	Actel的FPGA受温度影响大吗？在不同的温度下受影响的有哪些性能？比如时延，频响等等
[答：Albert_Tai]	EVERY semiconductor device affected by temperature, not just Actel FPGAs. On the other hand, Actel"s FPGAs has excellent performace in extreme temperature conditions	[2004-9-29 11:15:45]
[问：dreamwalkers]	在您所介绍的增量设计中，旧模块的性能是被完全保留的，是吗？如果用固定旧模块的方式来进行增量，那在设计之初必须对工程进行详细而且富有预见性的模块划分吧？
[答：Albert_Tai]	A well planned design is always required not just limited to incremental flow. Incremental flow is just a useful tool to help the designs to reduce the overhead in design iterations	[2004-9-29 11:18:46]
[问：xeron]	请问Actel Ax系列是否支持全局复位？能否保证加电时内部所有r-cell同步清零？
[答：Albert_Tai]	Yes, it does.	[2004-9-29 11:19:36]
[问：ecnan jing_EBY7E]	ACTEL的FPGA是否支持内部多电源系统？
[答：Albert_Tai]	Actel Axcelerator family supports mult-standard I/O, and mix different I/O voltages on the same device.	[2004-9-29 11:20:25]
[问：senlinchen]	增量设计是否仅仅需要逻辑综合工具的支持就行了？
[答：Albert_Tai]	No, as mentioned in the presentation, the back-end place & route tool is the key in incremental flow	[2004-9-29 11:21:16]
[问：boyfly]	请问actel的pll是模拟的还是数字的，对处理时钟抖动效果如何？我用别家的pll时，发现只是分频，倍频，锁相还行，却不能改善抖动，不知道actel的如何？
[答：Albert_Tai]	It is an analog PLL. In fact, PLL is not used to improve jitter, it will only intorduce more jitter to the source. It is true for any PLL. To keep the jitter minimal, you need to have a low jitter input.	[2004-9-29 11:23:30]
[问：dreamwalkers]	Actel的CPLD支持将下载内容回读的功能吗？
[答：Albert_Tai]	Actel"s produce is FPGA in architecture, which is different from CPLD. Actel"s FPGA can effectively prevent its content from being read-back, once it is secured.	[2004-9-29 11:25:06]
[问：brotherjam]	does actel fpga family support internal tri gate. If not ,how to solve this problem?
[答：Albert_Tai]	No. Internal multiplexer has the same functionality	[2004-9-29 11:25:58]
[问：senlinchen]	What do you mean when you say "Static timing analysics tools"? Software or hardware?
[答：Albert_Tai]	It is a timing analysis software. Actel"s back-end software, Designer also includes this tool. It is called Timer	[2004-9-29 11:26:40]
[问：fatfox]	现在是否可以得到免费版或者评估版的actel开发软件?最新的版本是否支持增量设计流程的功能?
[答：Albert_Tai]	Yes, you can. You can contact your closest distributor to get one!	[2004-9-29 11:27:13]
[问：sfm7739]	请问ACTEL的增量设计和ALTERA的LOGICLOCK增量设计是相同原理吗？
[答：Albert_Tai]	Yes, they are similar	[2004-9-29 11:28:00]
[问：dreamwalkers]	Actel的PLL能接受的时钟最高频率是多少？
[答：Albert_Tai]	APA family: 180MHz Axclerator family: 1GHz	[2004-9-29 11:28:33]
[问：harry2004]	synplify 现在的版本最高是多少
[答：Albert_Tai]	7.7	[2004-9-29 11:29:01]
[问：aglalala]	请问,有哪些产品是针对电子器具/消费以及通信基础构造应用的低成本、低功耗ASIC替代方案?
[答：Albert_Tai]	APA family (for medium to large gate count applications) eX and SXA families (for small to medium gate count applications) Axcelerator family (for large gate count and ultra-fast applications)	[2004-9-29 11:31:01]
[问：boyfly]	有个地方不明白请教一下：平时说的后仿真和静态时序分析是什么关系，既然说静态，那有没有动态呀，能否给介绍一下？
[答：Albert_Tai]	Post-layout simulation is for dynamic timing verification. Its is useful to verify the functionality of a design, but it heavily depends on the coverage of the testvector. While, static timing analysis can detect any potential timing problem and not any require testvector	[2004-9-29 11:33:01]
[问：liup]	设计中多时钟怎么处理，一些信号如读、写是否也可以处理为时钟？？？
[答：Albert_Tai]	All high loading signal can be routed with global network to take advantages of its high speed and low skew features	[2004-9-29 11:34:04]
[问：aglalala]	中国的销售处如何进一步联系呢?
[答：Albert_Tai]	Which city are you in?	[2004-9-29 11:34:20]
[问：wtfeng]	Can you introduce the main use of FPGA in the Auto-electronics?Thanks
[答：Albert_Tai]	fuel injection control safty air-bag control wireless communication and many more...	[2004-9-29 11:36:02]
[问：wyattwww]	ACTEL的FPGA与其他品牌相比（ALTERA）最大的特点是那些？
[答：Albert_Tai]	Single chip Live at power-up High security High reliability High logic utilization Soft-error resistance Low power	[2004-9-29 11:37:24]
[问：smiec]	我是FPGA的新用户，能否提供相应的入门与提高的书籍或者资料，使我能尽快学习和使用FPGA，非常感谢各位老师专家。
[答：Albert_Tai]	Please send me an email, I"ll introduce a book: albert.tai@actel.com	[2004-9-29 11:37:58]
[问：aglalala]	MX FPGAs的售价是多少？如何获得详细资料？
[答：Albert_Tai]	Please contact our local distributor for the pricing and more detail information	[2004-9-29 11:38:20]
[问：liup]	在芯片内命令解码是如何实现的，有比较成熟的结构吗？？？
[答：Albert_Tai]	What kind of command (or coding scheme) are you talking about?	[2004-9-29 11:38:55]
[问：huangxinhua]	希望能得到更具体的书面资料,请问如何可以获得?谢谢!
[答：Albert_Tai]	Please send me an email: albert.tai@actel.com	[2004-9-29 11:39:14]
[问：liup]	一般要求用寄存器信号输出，如用各种门或比较器等会出现什么情况？？？
[答：Albert_Tai]	In fact, it all depends on the timing requirement. Registered output will ensure minimal clock-to-out timing. It will also produce and glitch free (clean) output signal.	[2004-9-29 11:40:30]
[问：lxmlxmlxm]	ACTEL Ax系列是否能设计异步单端口RAM，Ax系列中的门数与逻辑单元个数是如何对应的
[答：Albert_Tai]	No, it only supports synchronous mode.	[2004-9-29 11:41:03]
[问：senlinchen]	Actel的FPGA目前主要的应用在哪些方面的产品中？
[答：Albert_Tai]	Consumer electronice mark, ASIC replacement market, industrial application, other high reliability applications	[2004-9-29 11:42:32]
[问：liup]	为什么有的芯片时钟输入到内部后进行分频再连到功能模块？？？此时寄存器模块的时钟是外部输入时钟还是分频后的时钟？？？
[答：Albert_Tai]	It is subjected to design requirement. Sometimes, using a internal divided clock can save logic resource and reduce power consumption. If a divided clock is used, it comes from internal clock dividing module.	[2004-9-29 11:44:09]
[问：xly6]	使用增量设计，会不会出现下面的情况：当设计的程序的容量超过所选片子的容量的90％时，由于软件对程序进行了优化（优化的过分了），导致编译能通过，但结果逻辑不对。
[答：Albert_Tai]	No the synthesis tool will know whether the design exceed the gate count of the target device. You will be able to detect it before place and route	[2004-9-29 11:45:23]
[问：cx_78]	乒乓结构能够缩短设计周期多少
[答：Albert_Tai]	It all depends on how frequent you modify your design, and it not quite related the the design"s architecture	[2004-9-29 11:47:13]
[问：ecnan jing_EBY7E]	增量设计出现的冗余，如何优化？
[答：Albert_Tai]	For most of the time, to maintain a compile point, the redundance at the block boundaries can not be optimized.	[2004-9-29 11:48:56]
[问：fatfox]	how can I get the information of the distributors in China ?
[答：Albert_Tai]	Please send me an email and the location of your company, I will assign a local distributor to help you out	[2004-9-29 11:49:43]
[问：senlinchen]	Thanks for all of your careful explanation. Can you explain static timing analysis in more detail
[答：Albert_Tai]	Static timing analysis based on the post layout timing database and the design constraints to analyze a design"s timing parameters like: register to register timng setup time hold time clock to output time input to output time clock skew	[2004-9-29 11:51:37]
[问：boyfly]	请问有没有什么消除抖动的方法？
[答：Albert_Tai]	Use a semiconductor device with minimal jitter factor (e.g. Actel"s eX family)	[2004-9-29 11:52:16]
[问：boyfly]	我感觉actel的fpga相对其他家好像更贴近asic一些！
[答：Albert_Tai]	Not necessary. Actel"s FPGA is a kind of general purpose programmable logic device and can be used in all kind of applications. But it is true that we have special advantage in ASIC conversion.	[2004-9-29 11:53:53]
[问：aglalala]	广州的销售处如何联系?
[答：Albert_Tai]	Please send me an email, and I will provide you more detailed information: albert.tai@actel.com	[2004-9-29 11:54:40]
[问：frzn110]	我正在进行用FPGA实现图像增强方面的研究，请问有相应的案例吗？
[答：Albert_Tai]	Yes, we have some customers in USA and Europe done similar design with our FPGA	[2004-9-29 11:55:30]
[问：boyfly]	能介绍一下流水线设计吗？我只是看到别人说过它的诸多优点，具体不太清楚！谢谢
[答：Albert_Tai]	Pipeline design is an effective approach that can help to reduce the clock cycle (or increase the speed) of a synchronous design. Basiclly, it insert registers between cominatorial logic block to break a long logic delay path to several shorter paths. It will however, increase the logic requirement and clock latency. And it needs more design effort.	[2004-9-29 11:58:00]
[问：flyfantasy]	请问Synplify Pro的通用版本（即适用于各厂商FPGA）是否也具有增量综合的功能？
[答：Albert_Tai]	The other public versions also has mulit-point synthesis feature but do not support Actel at the moment.	[2004-9-29 11:59:05]
[主持人：ChinaECNet]	恭喜您，北京讯风光通信技术开发有限责任公司的boyfly经过电脑抽奖您在本次座谈中获得一部MP3播放器。请网名为boyfly的用户与中电网联系(8610-82888222-7009 或 lilin@chinaecnet.com)。	[2004-9-29 12:03:02]
[主持人：ChinaECNet]	在此，中电网特别感谢给予本次中电网在线座谈巨大支持的Actel公司，特别感谢专门在线回答各位听众（网友）提问的Actel公司的各位专家们，特别感谢各位听众（网友）积极热情的参与。祝大家事业有成、生活愉快！欢迎多提宝贵意见，欢迎关注中电网，下次再见。	[2004-9-29 12:03:15]

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