| 主题:使用MAX II CPLD降低系統成本節省開發時間 |
| 在线问答: |
| [问：Anoymous] |
What are the reference prices? |
| [答：Susan] |
Galaxy will give you more detail pricing information after this
seminar. Thanks. |
[2004-4-6 10:29:51] |
| [问：Anoymous] |
您好,我每次在設計的時候,如果把CPLD的marco
cells容量用盡,在Run時發現溫度總是過熱,大約在60~70度左右,非常燙手,是否在組譯或設計程式時有設定需注意的?或者這樣的高溫屬於正常呢? |
| [答：Andy] |
Hi,請問與你CPLD相接的IC是否消耗非常多的電力? |
[2004-4-6 10:31:06] |
| [问：tanzhirong1] |
MAX
II的市场定位在哪个层次？估计用户使用它做设计的成本是多少 |
| [答：Andy] |
它主要是做為不同device間的的介面,或I/O expansion,address
decoding或是不同電壓準位間的信號當需要做轉換時另外,可用maxii與一個flash來取代傳統的configuration
device. |
[2004-4-6 10:37:09] |
| [问：chengates] |
使用AHDL於MAX+plusII10.2COMPILER過的檔案,可否直接相容於MAX
II CPLDs |
| [答：Andy] |
Dear Sir,MAXII device only support QuartusII.you have to
recompile in QuartusII. |
[2004-4-6 10:38:05] |
| [问：ritashih] |
若原本為acex1k的design,可否完全移植至MAXII架構裡?
有否需修正的部分? |
| [答：Elliott] |
This is must by design,but all most can mageration to
MAXII. |
[2004-4-6 10:41:25] |
| [问：pantinjin] |
我不知道怎样把底层做主层来走线，并改变走线的大小。 |
| [答：Andy] |
Dear Sir,about the routing,quartusII40 can provide best result
automatically.if you need to improve the result,you can adjust
settings in QuartusII.you can leave your tel number to
kevinc801@gfec.com.tw |
[2004-4-6 10:41:57] |
| [问：qzhu] |
I hope to hnow the max speed of MAX II CPLD
and resouce. |
| [答：Andy] |
Dear Sir,because the MAXII is a all new architecture with
newest .18um process.so,it can provide 200Mhz performance and very
efficient resource usage.anyway,the Fmax is depend on your design
size,architecture, even coding style. |
[2004-4-6 10:44:32] |
| [问：dboyman] |
MAX II
CPLD在开发大规模集成电路系统时，与VHDL等描述语言结合ASIC比较好象优势不是太明显，怎样取舍它们！ |
| [答：Andy] |
Dear Sir,actually,QuartusII40 can support VHDL,AHDL,Verilog and
schematic. but, ASIC design flow only supports pure VHDL and
Verilog.if you will transfer design to ASIC flow,i suggest you to
write "pure" VHDL or Verilog.in addition, MAXII can provide lowest
cost. i don"t suggest you to transfer CPLD design to ASIC. |
[2004-4-6 10:49:20] |
| [问：luker112] |
现在已有QUARTUS，那麽用MAX II 还有什麽优势呢 |
| [答：Elliott] |
MAXII"s feature Low power, High density, User flash
menory,ISP,MultiVolt coreMultiTrack Interface,MultiTrack
Interconnect. |
[2004-4-6 10:50:51] |
| [问：Renlisheng] |
1. MAX II CPLD开发工具价格？2. MAX II
CPLD芯片价格？3. MAX II CPLD同级芯片优缺点比较？ |
| [答：Hugh] |
MAx II CPLD"s FeatureLow PowerHigh DensityUser Flash
MemoryReal-Time-In-System Programmability(ISP)MultiVolt
CoreMultiVlot I/O InterfaceMultirack interconnect, JTAG
Translator. |
[2004-4-6 10:52:09] |
| [问：mi040606] |
What is the difference between PLD and
CPLD? |
| [答：Susan] |
PLD is general term for all programmable logic device. CPLD
is complex programmable logic device. It has instant on,
non-volatile and reprogrammable, single chip features. |
[2004-4-6 10:52:33] |
| [问：boblin0319] |
MAX-II 支持LVDS嗎? 操作速度可以有多快? |
| [答：Andy] |
Dear Sir,maxII only suppot TTL,CMOS,PCIthe operating speed
is depend on design. |
[2004-4-6 10:53:09] |
| [问：张振坤] |
如何消除组合逻辑产生的毛刺? |
| [答：Andy] |
Dear Sir,you can refer to some digital design textbook.for
example: if a FSM"s state translate has glitch,you can adjust the
state encoding. |
[2004-4-6 10:55:16] |
| [问：qin] |
在芯片封装表中，标注长度为9.00BSC, BSC表示什么意思? |
| [答：Elliott] |
BSC is Basic Spacing between Centers |
[2004-4-6 10:55:26] |
| [问：eikijoe] |
我的電路設計上與CPLD相接的地方並無消耗許多電力,同樣的設計,我只要不把marco
cells的容量寫滿,就不會很燙,但是一寫滿以後,就幾乎可以煮蛋了 |
| [答：Andy] |
Dear Sir,did you try the design in different device?and, i
think your problem can be solved by adjustsynthesis or fit
setting. |
[2004-4-6 10:56:40] |
| [问：happyfish] |
新產品比一代產品有什麼不一樣，多了什新功能 |
| [答：Matte] |
Low Power,High Density,User Flash Memory, ISP,MultiVolt Core,Multivolt
I/O interface,MultiTrack Interconnect,JATG Translator. |
[2004-4-6 10:57:15] |
| [问：qin] |
CPLD器件在多时钟系统设计中有何特别的注意事项? |
| [答：Elliott] |
1.Don.t use geted clk2.Need to use global clk |
[2004-4-6 10:58:15] |
| [问：xyuding] |
相对于很多的IO而言，LE少了些。max2或许只能用于特殊场合。 |
| [答：Susan] |
MAX II is CPLD product, which targets low to mid density range
designs. Also for most of CPLD applications are bus bridging,
I/O expansion etc. They requires more I/O than
LE. If you need more LE for your design, please refer our FPGA
(Cyclone or Straix) families. |
[2004-4-6 10:58:56] |
| [问：liu-0315] |
How about the speed of the MAX
II? |
| [答：Andy] |
Dear Sir,the operating speed is depended on
design,architecture, coding style... |
[2004-4-6 10:59:01] |
| [问：wjl27] |
我使用的是MAXPLUS 2软件,而非QUARTS
,那么能否在MAXPLUS上使用?现在能否提供样片? |
| [答：Matte] |
Not,The MaxPlusII not support the MAXII. |
[2004-4-6 10:59:46] |
| [问：RockHuang] |
請問貴公司的客戶以CPLD量產時，實際良率大概多少？ |
| [答：Andy] |
Dear Sir,Sorry Sir,yield rate is the confidential data of a
Fab. |
[2004-4-6 10:59:53] |
| [问：jack] |
請問 MAX II 是否可看成小型的 FPGA + Download Flash ?
或者和一般 FPGA 最大差異為何? |
| [答：Elliott] |
Yes,它可以當成一般小型的FPGA |
[2004-4-6 11:02:19] |
| [问：brianaltera] |
Does MAXII use byteblaster or byteblaster II
as programming adapter? |
| [答：Matte] |
Yes,MAXII is using byteblaster or byteblasterII to download. |
[2004-4-6 11:02:49] |
| [问：onlooker1] |
请阐述CPLD在组合逻辑与时序逻辑设计方面的优劣 |
| [答：Andy] |
Dear Sir,in MaxII, it uses cyclone-liked architecture.the
basic logic element can provide a 4 input LUT and a register.and
dedicated carry out generation, LUT,Reg chainsare provided to improve
the compilation result. |
[2004-4-6 11:02:51] |
| [主持人：ChinaECNet] |
各位觀眾，現在用戶提問很踴躍，專家正在逐一回答。請耐心等待您問題的答案，同一問題請不要多次提交。 |
[2004-4-6 11:03:46] |
| [问：mi040606] |
What is the main advantage of the CPLD and
FPGA?Which one is better in cost and performance? |
| [答：Susan] |
It depends on what is your design. For FPGA, it has rich
register resource and has more LE, normally it targets larger, complex and
requires a lots of registers designs. If your design needs more
logic, like decoder, than CPLD will be better. CPLD has
advantage at instant on, single chip, and non-Volatility. FPFA
has advantages at high desnities, embedded SRAM, PLLS and IP. |
[2004-4-6 11:05:28] |
| [问：mi040606] |
How to use the built-in flip-flop in CPLD
for storage data? |
| [答：Andy] |
Dear Sir,you can write/draw the register in your design.if you
needs memory, QuartusII will use logic element to implement your
memory.in addition,the MAXII can provide user flash,you can use it
to store some data. |
[2004-4-6 11:05:53] |
| [问：Anoymous] |
請問參考價格 |
| [答：Susan] |
We will contact you and provide you more detail pricing
information. |
[2004-4-6 11:05:53] |
| [问：谢文志] |
请介绍one-hot状态机与Binary/Gray状态机的特点? |
| [答：Andy] |
Dear Sir,binary can save most register.onehot can provide best
speed but uses most register.gray can provide a trade off between
onehot and binary. |
[2004-4-6 11:07:29] |
| [问：liu-0315] |
How many of LE in MAXII?What is the price
for each LE? |
| [答：Susan] |
The LE range for MAX II is from 240 LE to 2210 LE. We will
contac you to provide more detail pricing information. |
[2004-4-6 11:07:50] |
| [问：liu-0315] |
What is application area for the CPLD and
MAX II? |
| [答：Matte] |
Consumer Products,Communication Products,Computing
Products,Battery-PoweredProducts and all logic control . |
[2004-4-6 11:07:54] |
| [问：qzhu] |
Can the LVDS signals is used on it with
speed 622MHZ? |
| [答：Andy] |
Dear Sir,maxii can"t use LVDS.you can use stratix or
stratixGX. |
[2004-4-6 11:08:11] |
| [问：kwqiang_2000] |
maxplus 10.2
baseline，仿真的時候碰到了一些麻煩，就是仿真時間只有1us，但時鐘步長竟然是200ns，也就是只有5個周期，太少了。有何辦法解決這個問題? |
| [答：Andy] |
you can turn on the File ==> End time to give longer value for you
draw the input waveformwhen you open the waveform file. |
[2004-4-6 11:10:15] |
| [问：Nike-040406] |
How much for the development kits of MAX
II? |
| [答：Susan] |
Our Quartus II web edition supports MAX II product and it is
FREE. Please go to www.altera.com to download the software and
request the license. Also you may contact Galaxy for CD of
software. But you still need to get the license from the Altera
Web. |
[2004-4-6 11:10:29] |
| [问：boblin0319] |
MAX-II 什麼時候可供貨 |
| [答：Susan] |
EPM1270 ES will be ready at July. EPM240 and EPM570 ES will
be ready at Oct. For all M/P devices will be ready the
beginning of 2005. |
[2004-4-6 11:11:51] |
| [问：bithxm] |
MAX
II目前在中国的供货情况如何，如果是小批量订货，周期大概多长 |
| [答：Susan] |
Altera just announced MAX II a month ago. The first silcon of MAX II
will be ready at July. For M/P devices will be ready the beginning of
2005. We will contact you for more detail ordering information. |
[2004-4-6 11:14:17] |
| [问：kwqiang_2000] |
dcfifo中的wrusedw[]和rdusedw[]是什麽?如何使用? |
| [答：Andy] |
Dear Sir,you can use the "documentation" tab in megawizard window
in QuartusII40.it can provide you the sample waveform and I/O port
definition. |
[2004-4-6 11:14:40] |
| [问：kwqiang_2000] |
請問如何在maxplusII中使用功能庫和IP核 |
| [答：Elliott] |
I suggest you to use Quartus II.You can use Mega-Wizard Plug-in
Manager to editor Altera library and Altera IP |
[2004-4-6 11:15:17] |
| [问：张振坤] |
Altera的哪个系列CPLD支持三态输出? |
| [答：Andy] |
Dear Sir,all CPLD families are provided.ex:
MAX3000,7000,MAXII |
[2004-4-6 11:15:33] |
| [问：kwqiang_2000] |
Altera的CPLD與FPGA相比有何優勢? |
| [答：Susan] |
For CPLD, it has instant on, low cost, ease of use, non-volatililty
and single chip features. For FPGA, it has high densities, fast fmax,
embedded SRAM, PLLs, and IP features. |
[2004-4-6 11:16:55] |
| [问：41070924] |
请问我使用CPLD实现8路24串行数据的并行转换，常规来说需要什么样级别的片子，如果我还想在CPLD上实现该数据FIFO缓冲呢？我用CPLD实现缓冲合适吗？ |
| [答：Andy] |
Dear Sir,you can consider the needed I/O number and FIFOsize
to choose a suitable device.CPLD can not provide the FIFO.
maybe,you can consider the cyclone EP1C3. |
[2004-4-6 11:17:48] |
| [问：qzhu] |
Is it compatible with 5V? |
| [答：Susan] |
No. For 5V design, it requirs other circuits to
help. We will provide the application note for how to use MAX
II for 5V design. |
[2004-4-6 11:18:06] |
| [问：kwqiang_2000] |
如何向LPM實現的RAM中寫資料? |
| [答：Matte] |
You can designers to generate a Memory Initialization File (.mif) to
initialize the ROM contents. |
[2004-4-6 11:18:45] |
| [问：hiarfu] |
MAX II對於功秏的降低方法 |
| [答：Andy] |
Dear Sir,MAXII uses new .18um process and a internal power
regular.so,the Vccint can be 3.3V , 2.5V even 1.8V.and, the
all new architecture and power management circuits provide a low power
consumption. |
[2004-4-6 11:20:21] |
| [问：kwqiang_2000] |
在verilog的書上找到一個非同步清零d觸發器的例子，在quartus中卻不能運行，請各位高手指點迷津，怎麽才能實現非同步清零? |
| [答：Andy] |
Dear Sir,could you provide your error message? |
[2004-4-6 11:21:00] |
| [问：netstraveler] |
以我對ALTERA產品的粗淺認知,我覺得MAX II在貴公司的產品定位應該是屬於law
cost的產品,那與擁有同樣低價優勢的Cyclone相比,它們之間有何差異? |
| [答：Susan] |
MAX II is low cost CPLD product and Cyclone is low cost FPGA
product. CPLD and FPGA are different products. FPGA
(Cyclone) has higer densities and rich register. CPLD (MAX II)
is logic rich, non-volatile single chip solution. From cost
poin of view, we can say that MAX II has lowest cost per I/O and Cyclone
has lowest cost per LE. |
[2004-4-6 11:21:47] |
| [问：mimouse] |
如何 vhdl,verilog 中实现双向开关? |
| [答：Elliott] |
Please go to http://altera.com/support/examples/exm-index.html,it
have example |
[2004-4-6 11:22:37] |
| [问：wjl27] |
MAX 2
的时间级别?他的时序逻辑能力对比FPGA的能力如何? |
| [答：Susan] |
The speed grade for MAX II are -3, -4 and -5. |
[2004-4-6 11:23:37] |
| [问：mimouse] |
我是近来才开始学cpld语言的，在使用mp2应用软件时，打开*。tdf文件进行EDIT；无论我是用VHDL，Verilog
HDL，ABEL 语言（都是些示例），总是没办法通过,为什么? |
| [答：Andy] |
Dear Sir,i would like to suggest you to use VHDL or
Veriloglanguage. |
[2004-4-6 11:24:03] |
| [问：brianaltera] |
Dear Sir: Could I use I2C
or SMbus to access the flash in MAXII? |
| [答：Elliott] |
It can use SPI , parrallel and user define. |
[2004-4-6 11:24:35] |
| [问：brianaltera] |
Could NIOS fit into MAXII?Is there
smaller NIOS available soon? |
| [答：Susan] |
No. Currently we do not plan for NIOS solution
into MAX II. We will contact you to discuss your needs for
NIOS. |
[2004-4-6 11:24:59] |
| [问：Oswin] |
請問一下QuartusII的在設計MAXII時是否可以直接由外部給予CLOCK,不經由global
clk輸入? |
| [答：Andy] |
Dear Sir,i strongly recommend you to use global clk or
dedicated input pins as clock input. |
[2004-4-6 11:25:07] |
| [问：eikijoe] |
在時序的邏輯設計裡,若我未將CLK接腳接至GLOBAL
CLK而接至一般的I/O腳位,會有什麼樣的問題發生? |
| [答：Andy] |
Dear Sir,it may cause clock skew problem. |
[2004-4-6 11:26:31] |
| [问：qzhu] |
Could you tell the max speed of
clock. |
| [答：Andy] |
Dear Sir,because the speed is decided by QuartusII compilation and
your design, please refer to the compilation report. |
[2004-4-6 11:27:40] |
| [问：ritas869] |
MAXII的I/O為何沒有208PIN 或 240PIN 的包裝,
一下子就跳到BGA的包裝了 |
| [答：Andy] |
Dear Sir,it is consider most customers" requirements andlowest
cost .... |
[2004-4-6 11:28:33] |
| [问：chenzhongwen] |
此芯片的价格是多少？100K时 |
| [答：Susan] |
We will contact you to provide more detail information about
pricing. |
[2004-4-6 11:29:28] |
| [问：谢文志] |
代替ISA的译码电路和通用I/0接口电路（8255）一共100个I/0口左右。请高手帮忙选一块Altera芯片。 |
| [答：Andy] |
How about EPM570 144 pin device?or you have other logics and pins
to fit in it....maybe you can choose bigger MAXII or cyclone
devices. |
[2004-4-6 11:30:26] |
| [问：Nike-040406] |
Can you tell us the design flow chart of
CPLD? Any difference for the FPGA? |
| [答：Matte] |
The CPLD and FPGA design flow all most same.PLD Design Flow :Design
entry-->Synthesis-->P&R-->Timing
Analysis-->Simulation-->Program & Test. |
[2004-4-6 11:31:16] |
| [问：cailiangliang1] |
通常情况下是将CPLD同DSP或单片机配合使用，基于CPLD功能较强的特性节省开发时间是可以理解的，但从何降低成本我不大清楚。谢谢！ |
| [答：Susan] |
CPLD can replace any logics funcations, even some small ASSP
devices. Base on current CPLD low price, we had studied that it
can help to reduce the cost for integrate all these functions. |
[2004-4-6 11:32:09] |
| [问：liu-0315] |
Can you tell us the security of the MAX
II? |
| [答：Elliott] |
Dear Sir,the security ability still be provided.and the
security should be better than max3000. |
[2004-4-6 11:32:30] |
| [问：ecnan
jing_EBY7E] |
CPLD能否实现ADC? |
| [答：Andy] |
Dear Sir,no. CPLD only provide you pure digital design. |
[2004-4-6 11:34:44] |
| [问：ljh9197] |
如何让MPII支持新的器件？ |
| [答：Elliott] |
Dear Sir,MaxII is used with QuartusII4.0. |
[2004-4-6 11:38:15] |
| [问：chengates] |
MAX II CPLDs 是否可工作在5v的介面 |
| [答：Susan] |
Yes. But it requires extra circuit to do it. We
will provide the application note for it. T |
[2004-4-6 11:40:50] |
| [主持人：ChinaECNet] |
現在座談即將結束。歡迎各位填寫線上座談頁面的問卷調查，並請于明天中午12點以前提交。本次 Ipad
抽獎將從填寫過問卷的工程師中抽取，謝謝。 |
[2004-4-6 11:41:23] |
| [问：tjshen] |
请问EPM7128的单价是多少？是否有更低价的类似芯片？SMT比同型芯片便宜多少？ |
| [答：Susan] |
You will contact you to provide more detail
information. MAX II family will be the better solution for your
new design, also it will save your cost. |
[2004-4-6 11:41:56] |
| [问：mi040606] |
How many hardware and software in Altera
development platform? |
| [答：Susan] |
For devices, we have MAX, Cyclone, Stratix, Stratix II
famlies.Also we have NIOS, and IP.For all products are
suuport by Altera software - Quaratus II. |
[2004-4-6 11:44:34] |
| [问：liu-0315] |
Where can I get the samples of MAX
II? |
| [答：Susan] |
Please contact our distributors. |
[2004-4-6 11:45:16] |
| [问：evins] |
Is
MAXII must collocate flash to replace Altera
configure devices ? ex: EPC2 |
| [答：Susan] |
MAX II is single chip solution, it does not need extra memory
device. |
[2004-4-6 11:46:17] |
| [主持人：ChinaECNet] |
本次線上座談結束後，中電網將請Altera公司的專家繼續答復所有的來自各位聽眾（網友）的提問，然後整理上載到中電網網站上，以便大家查閱。 |
[2004-4-6 11:47:19] |
| [主持人：ChinaECNet] |
在此，中電網特別感謝給予本次中電網線上座談巨大支持的Altera公司，特別感謝專門線上回答各位聽眾（網友）提問的Altera公司的各位專家們，特別感謝各位聽眾（網友）積極熱情的參與。 |
[2004-4-6 11:47:35] |
| [主持人：ChinaECNet] |
祝大家事業有成、生活愉快！歡迎多提寶貴意見，歡迎關注中電網，下次再見。 |
[2004-4-6 11:47:42] |
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