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[问:deyun] 现在的CPLD在AD转换方面性能如何? 
[答: Dawson] CPLD是数字逻辑器件,目前还不能实现如AD转换这样的模拟功能.  [2003-5-15 10:41:20]
[问:TI] 我选用了CPLD,她的安全到底有多高?千门级别。 
[答:Rock] 在cpld 里写入加密位就可以实现器件加密,大门数(500-1000gates)的cpld基本无法解密  [2003-5-15 10:42:46]
[问: leonqin] 现在Cyclone的国内供货情况怎样 ,对于小批量(<1000pcs),价格是否相对同等LE容量的ACEX系列有优势? 
[答:Singer] At present, delivery time is short 3-4 weeks is possible and up to customer requirement .For small qty like 1000pcs, may up to ACEX depends on application .  [2003-5-15 10:43:20]
[问: hwj2008] 进行FPGA设计,经常需要向其它芯片提供时钟,这时将涉及提供时钟反馈的问题,具体有没有高一点的好方法? 
[答:Ivan] During FPGA design, both the PLD itself and other device need clock signal from outside. Our FPGA has PLL which can receive clock and output it, which has several feedback circuit. These circuit will help you to adjust the phase and frequency. You can also get the clock from clock chip directly and don"t need to go through the FPGA as you like.  [2003-5-15 10:44:10]
[问:leonqin] 请问在下一个QuartusII版本中,是否会支持MAX7000S系列? 
[答:Ivan] 是的, QII 3.0就可以支持了。  [2003-5-15 10:45:21]
[问:Anoymous] 在使用maxplusII时发现,当选择芯片epm7512aeqc208-10时无法适配成功,但是选用auto时却发现epm7512aeqc144-10等芯片都可以适配成功,但是epm7512aeqc208-10却还是没有成功,这是何故,该如何解决? 
[答:Ivan] You need to check the MaxplusII version, it should support the device. You can contact our distributor to help you on this.  [2003-5-15 10:57:58]
[问:deyun] 我了解的10K30等都比较贵,请问低成本的CPLD指那些芯片,价格和性能和10K30相比有何优势? 
[答:Singer] For CPLD, price is very competitive and better than 10K30.Now, as CPLD has a lot of improvement in function, more and more application has started to use low-cost solution and shorter time for development .  For more details, pls contact Qiupei at 0755 83592920-556 .  Thanks .  [2003-5-15 10:58:11]
[问:zzxpj] 请介绍FPGA和CPLD的适用范围和入门开发工具。 
[答:Rock] fpga/cpld 的应用范围比较广,只要是数字信号出现的地方都可能发挥他们的作用.可以覆盖通信,医疗电子,消费类......运用可编程器件可以灵活的方便我们的设计,同时可以大幅度提高系统设计的性能.采用ALTERA MAX3000A(CPLD)和Cyclone(FPGA)同时可以获得低成本的解决方案.开发工具有Maxplus(容易上手) 和Quartus(功能强大).  [2003-5-15 11:00:20]
[问:wy56] 请问:低成本的FPGA和CPLD方案在网络上的应用,目前在商品化产品上达到了何种程度?是否可以实现USB Host功能?以太网的接口可以达到100M的速度吗?另外,在数字视频和图像压缩方面有哪些成功的商品化应用方案? 
[答:Ivan] Yes, our Cyclone and Max 3000 device have lots successful story both in china and foreign, in most of  telecom application, USB, Ethernet and HDTV, PDP, MPEG4.... You may visit our web to view the example.  [2003-5-15 11:00:21]
[问:windhxc] 贵公司的EPF10K30E手册上说,可以用它来构造双端口RAM但,我在实际的使用时发现,它并不能支持标准的端口,用它构建的双断口延时长达3个时钟周期,请问我应该怎么用它来构建标准的双端口RAM。谢谢! 
[答:Dawson] EPF10K30E的EAB(专门的存储单元)能支持简单的双端口的RAM(分开的读写地址和读写使能控制),如要实现真双端口的RAM,它会用多个EAB组合实现.CYCLONE器件具有我们最先进的RAM功能,能很好的支持真双端口功能.  [2003-5-15 11:00:26]
[问:Ano ymous] 是否有好的fpga的仿真系统可供参考! 
[答:Bill] 如果你使用Altera公司的PLD产品,你可以使用Altera的开发软件Maxplus II 或者Quartus II进行仿真,Altera也提供OEM版本的ModelSim,其他比较常用的仿真工具有Modelsim,VCS,NC-Verilog,NC-VHDL,NC-Sim我们的器件都可以支持。谢谢  [2003-5-15 11:01:17]
[问: 杨_64J7U] 目前,ALTERA公司的FPGA、CPLD的开发软件是什么? 
[答:Bill] 目前我们的开发软件有Maxplus II 和Quartus II.  [2003-5-15 11:01:37]
[问: hwj2008] FPGA设计低电压集成电路时应注意什么? 
[答:Jing] There are quite a few things to be considered when doing an FPGA design.  For example, physically, you should consider the the i/o standards(lvttl, lvds, lvcmos, etc), core voltgae of your board.  Logically, you should consider what fmax your design should be, how many resources you would use (e.g. Logic Elements, RAM blocks, I/O"s), how many clock domains you would have and how you should design your clock scheme, etc.  In the perspective of design guidelines, you should avoid asynchronous paths in FPGA design; well name your design modules according to their functionaly as well as their clock scheme.  This is very helpful in the design optimization stage, since you can easily find the nodes and add logic assignments.  One key thing is FPGA design is you should be familiar with timing calculations, e.g. Fmax, Tsu, Tco, Thold.  You should also be aware that timing is both affected by logic levels and place&route.  These are only some of the considerations for your reference.  There are much more that cannot simply be answered here.  [2003-5-15 11:02:02]
[问:wenbin _RA27Q] sopc的这一套开发工具要多少钱? 
[答:Singer] During this promotion period, Nios board at USD 495/set . Outside this period, price will get higher . So, pls order now for better price and delivery .  [2003-5-15 11:02:18]
[问:shixt47] 我设计的电路,在模拟部分采用+-3v电源供电(4节AAA),在后级数字部分想还是利用这4节电池供电,但又必须是+5V单电源。1.如何解决接地的问题?2.如何保持+5V? 3.这样可行吗? 
[答:Ivan] You may need to add one more DC chip( Power chip) for convert from 3V to 5.  [2003-5-15 11:02:41]
[问:ecnan jing_EBY7E] Cyclone 有多少IO口? 
[答:Rock] 视器件容量和封装不同,Cyclone 可以提供io数量65-301个.  [2003-5-15 11:03:15]
[问:TI] 我想用cyclone EP1C6.我关心的主要市成本问题。定购量到多少Altera可以提供HARDCOPY服务,每片的成本可以到多少! 
[答:Paul chan] EP1C6 will be the lowest cost 6,000 FPGA device. The exact price will depend on quantity and timeframe. For price quotation, please contact Arrow.Also, Cyclone will not be available in HardCopy because it is already cost effective compared to ASIC or ASSP.HardCopy will be available for higher density Altera FPGA families. Minimum Order Quantity (MOQ) will depend on the actual device density and quantity.  [2003-5-15 11:04:41]
[问:yu-sc@] 请简要介绍一下贵公司的Cyclone FPGA,MAX3000A CPLD, Nios 嵌入处理器和Quartus II网络版软件开发工具进入中国大陆的时间、预期的市场开发时间及用户可持续性应用时间。 
[答:Singer] For tooling on Cyclone and Nios, the time start from this year beginning ,probably in March and April .Normally customer uses around 4-8 weeks for development .  [2003-5-15 11:04:46]
[问:leonqin] 请问对于Cyclone系列来说,供电有什么特殊的要求VCCIIO、VCCINT有上电顺序要求吗? 
[答:Jing] The answer is No.  All Altera FPGA"s, including Cyclone, are hot-socketable,which means you can plug and unplug device while the power is ON, without damaging the device, and there"s no requirement on the order power-up for VCCIO and VCCINT.  [2003-5-15 11:05:35]
[问:xuemei zhao@] 51MCU扩展全双工串口可否用CPLD来实现,如何实现。 
[答:Rock] 完全可以.根据你的串口功能强弱,可以选择不同容量器件,若选用cpld,可以考虑MAX300A系列.  [2003-5-15 11:06:10]
[问:willam _gann1] ALTER 的低成本方案是否以牺牲性能为代价? 
[答:Jing] No.  Cyclone are designed based on the concept of high performance and low cost.  [2003-5-15 11:07:00]
[问:apple 163] 什么是Cyclone 器件系列? 
[答:Ivan] Altera's new Cyclone device family is the world's lowest-cost FPGA. Designed to make the benefits of programmable logic more accessible to a broader market, Altera developed Cyclone devices specifically for high-volume applications that previously were driven by cost pressures to standard products or ASICs. The Cyclone device family has the perfect mix of features, density, and performance at less than $1.50 per 1,000 logic elements (LEs)-half the cost of competing FPGAs. Finally, system designers building high-volume applications in the consumer, communications, computer peripheral, industrial, and automotive markets now have access to the flexibility, economic efficiencies, and time-to-market advantages of programmable logic. With densities ranging from 2,910 to 20,060 logic elements (LEs), Cyclone devices are optimized for maximum logic capacity at the lowest cost. Cyclone devices feature up to 288-Kbits of embedded memory, phase-locked loops (PLLs), and support for external memory interfaces and differe  [2003-5-15 11:07:19]
[问:apple 163] 设计Cyclone器件系列有什么准则? 
[答:Ivan] Altera included hundreds of customers from different market segments in the product definition process to identify price threshold, features, and performance required to address high-volume applications. In addition, Altera used a ground-up approach to design the Cyclone device family, using the same methodology that was used to define the Stratix™ device family. The result is Cyclone: the lowest cost FPGA ever with right mix of device capabilities.  [2003-5-15 11:09:58]
[问:li yicheng] 请问在用Nios设计(包括用户定义模块)的时候,有没有推荐的一个好的设计流程(是使用.bdf文件形式的模块框图还是采用HDL的实例化方法).并简要介绍与第三方工具的搭配使用问题. 
[答:Ivan] You can use .bdf as the top project file that could be more convenient to view all your project structure. But use HDL to make design could be easier to interface to third party tools. But even use BDF file, our QII may help to convert the file to HDL file to interface third party tools.  [2003-5-15 11:10:05]
[问:yu-sc] 我是否现在就可以获得免费的Quartus II网络版软件开发工具? 
[答:Rock] 为方便广大工程师的设计,可以从altera 网上download免费的QUARTUS2,他支持绝大部分器件的设计.  [2003-5-15 11:10:15]
[问:hddeng] 请问:如何在调试中察看EAB(例如用做FIFO或RAM时)中的大量数据,什么软件能做到这一点? 
[答:Jing] You can view the data in EAB by using SignalTapII, which is an embedded Logic Analyzer.  Our software QuartusII could automatically add SignalTapII circuit into the device and output interal data to the QuartusII GUI for easy debugging  [2003-5-15 11:12:04]
[问:da emony] 请从应用的角度谈谈CPLD和FPGA的不同? 谢谢 
[答:Bill] EPLD的容量一般比较小,比较适合做一些容量不大,组合逻辑比较复杂但是寄存器用的比较少的设计,如地址译码,总线接口逻辑,上电复位逻辑等,而FPGA的容量比较大,包含有大量的逻辑单元,内嵌存储器以及一些其他的高级特性,如锁相环,LVDS等,适合一些比较复杂的时序逻辑的应用之中,比如嵌入式cpu,数据处理等  [2003-5-15 11:12:12]
[问:sun yaguang] 1:从ALTERA什么规格芯片开始能实现芯片倍频功能。2:ALTERA是否提供了IP核功能介绍,价格为多少? 
[答:Singer] We have IP Core provided and price could be checked with our sales people in shenzhen .Pls call qiupei at 0755 83592920 -556  [2003-5-15 11:12:20]
[问:apple 163] Cyclone器件系列的主要用在那些市场领域? 
[答:Ivan] The Cyclone device family is the optimum low-cost solution for high-volume applications in a wide variety of markets including high-end consumer electronics, leading-edge communications, computer peripherals, industrial, and automotive. Cyclone devices provide a number of features optimized for volume applications such as plasma display panel modules, mid-range and low-end routers, and automotive electronics systems.  [2003-5-15 11:12:42]
[问:sdlmg] 请问最新的BYTE BLASTERII 电缆会不会提供原理图 
[答:Edgar] Yes.  We have provided schematics of BYTE BLASTER II.  Please contact your local Altera distributor for the schematics.  [2003-5-15 11:12:47]
[问:RED CLOUD] 什么类型的FPGA/PLAD可以实现简单MCU比如PIC16C54什么类型的FPGA/PLAD可以实现标准MCU比如8052什么类型的FPGA/PLAD可以实现简单16位DSP比如TI32XX网站上有样例设计吗?如何获得帮助?
[答:Ivan] You can use our Cyclone+ Nios solution for your application. You can access our web or contact our distributor to find the example or reference design  [2003-5-15 11:14:44]
[问:sfm 7739] 有有关在FPGA内使用nios或嵌入式ARM922使用的中文文档吗? 
[答:Bill] 我们目前的技术文档都是英文的,不过如果你在使用和阅读之中遇到什么困难可以联系我们的技术支持给您帮助  [2003-5-15 11:14:46]
[问:helen.xu] FPGA and CPLD can be used in which field? 
[答:Paul chan] Both FPGA and CPLD are programmable logic devices that can be used in all fields (e.g. market segments such as wireless & wired communication, consumer, industry, and automotive. However, their architecture is very different, FPGA is LUT based and CPLD is macrocell based. Its usage depends on the application. For example CPLD is normally used for combinatorial logic designs such as address decoding or simple logic control designs.  [2003-5-15 11:15:13]
[问:RED CLOUD] 芯片对工作电压纹波等参数有何要求? 
[答:Bill] 您可以参考具体的芯片的数据手册,其中有一项列出的芯片工作时建议的操作条件。可以得到具体的参数。  [2003-5-15 11:18:09]
[问: apple163] 为什么说,Cyclone器件系列很适合代替ASIC? 
[答:Ivan] Cyclone devices enable the development of new, programmable solutions in volume-driven applications where FPGAs were once considered too expensive. ASICs have high non-recurring engineering (NRE) costs, expensive design tools, and significant overall risk in bringing products to market in a timely manner. The historical price gap between a FPGA and an ASIC meant that a customer could recover the ASIC NRE charges at volumes near 10,000 units. The crossover point is anywhere from 100,000 units to 5 million units. Now system designers have access to the benefits of programmable logic-at ASIC prices.  [2003-5-15 11:18:12]
[问:Anoy mous] 我将选用CYCLONE 器件EP1C6Q240C6,我先想知道一点,它大概的价格是多少? 
[答:Singer] Price will be below USD 60 and negotiable upon yr qty .  [2003-5-15 11:18:49]
[问:tan- lin493@] FPGA与CPLD其工作方式与单片机的区别 
[答:Dawson] 单片机的指令有固定的执行方式,至少需要四个时钟周期.且时钟频率较低.PLD(FPGA & CPLD)的运算执行方式,会根据你实现该运算的硬件电路方式不同而不同.通常其运算的速度会远高于单片机.  [2003-5-15 11:18:51]
[问:Anoy mous] 在选择和DSP搭配使用时,什么时候用CPLD,什么时候用FPGA比较合适? 
[答:Edgar] For low density DSP processor control signals distribution, address decoding, use CPLD.  For complex DSP processor interfacing with external ASSP, use FPGA.  Or if you need to implement DSP coprocessing function, FPGA is more suitable as it can implement more DSP related fucntions such as mulitplier, accumulator, shift-register, etc.  [2003-5-15 11:18:55]
[问:TI] 我想知道贵公司配置器件的一些相关问题,比如:配置器件的编程方式,如何利用MAXPIUSII编程以及器件的一些电原理图等。 
[答:Ivan] You may get many help from the application note at "AN116", which has more detail description about altera device configuration.  [2003-5-15 11:19:14]
[问:hu- jian-li] CPLD的开发费用较大,请问有什么较好的方法减少开发费用和缩短开发周期? 
[答: Paulchan] For CPLD, Altera"s MAX 3000A is developed for the high volume market, so making it one of the lowest cost CPLD in the market. The exact price will depend on quantity. As an example, EPM3032 (32 macrocell) device will be less than USD1.0. The leadtime will depend on the exact device, and typically be in the 4 weeks range.For details, please contact Altera distributor, Arrow China.  [2003-5-15 11:20:03]
[问: engineer] Cyclone器件系列大批量的价格是多少? 
[答:Ivan] High-volume pricing (250,000 units) in 2004 for the EP1C3, EP1C6, EP1C12, and EP1C20 devices in the smallest package and slowest speed grade will start at $4, $8.95, $25, and $40, respectively. Pricing for 50,000 units in mid-2003 for the EP1C3, EP1C6, EP1C12, and EP1C20 devices in the smallest package and slowest speed grade will start at $7, $17, $35, and $60, respectively.   [2003-5-15 11:20:54]
[问: engineer] 什么时候可提供第一个Cyclone器件? 
[答:Ivan] Engineering samples of the first Cyclone EP1C20 and EP1C6 devices will be available in January and February 2003, respectively. The EP1C3 and EP1C12 devices will subsequently be available in April 2003. All family members will be in full production in the first half of 2003.  [2003-5-15 11:21:10]
[问:li yicheng] 在quartus中,是否可以在一个project总同时使用EDF(比如说产生Nios模块)和VQM(一个顶层模块,包括其他的一些功能模块)两种方式,如果可以的化,那在compile 设置是怎样制定其工具呢(edf和vqm是由不同的第三方工具产生的). 
[答:Edgar] Actually, the compiler setting is for top level module.  For lower level modules, Quartus can automatically detect the synthesis tools. If you open edf and vqm file, you can find synthesis tool"s information (such as synplify and leonardo spectrum), Quartus can automatically read this information and compile the netlist appropriately.  [2003-5-15 11:22:07]
[问:willam _gann1] 我使用ALtera的FPGA和CPLD已经有3年了。现在最没有把握的事情是,一个项目来了以后,我选择的FPGA的速度能否满足要求。因为有时项目很急,不容许先做计算机仿真就必须把硬件搭起来了。我想知道如何预先评估FPGA在速度方面能否满足要求? 
[答:Bill] FPGA的实际运行速度很大程度上取决于客户的设计,不同的设计方法对于同样的功能也有可能得到不同的速度。一般我们都希望客户首先用软件进行时序分析或时序仿真,然后才进行硬件的设计和制作。  [2003-5-15 11:22:25]
[问:tom soft] 因为我们需要使用Cyclone用做下一个项目的开发,但不知道在国内那里可以购买到这个芯片,另外EP1c6的大致价格是多少?谢谢!!! 
[答:Singer] Dears,Arrow is the Distributor of Altera In China .  So, you could contact us for price and details .Pls send email to me at or dial0755 83592920 -556 call Qiupei .  Thanks .  [2003-5-15 11:23:12]
[问:sales] Cyclone器件是否和ACEX®和Stratix器件在引脚上兼容? 
[答:Ivan] No, Cyclone devices are based on a completely new architecture and are not pin compatible with Altera's existing ACEX or Stratix devices.  [2003-5-15 11:24:00]
[问: REDCLOUD] 如何使用在片PLL作为芯片工作时钟?
[答: Dawson] 你可通过我们软件中的Megawizard中的altpll来利用我们的pll.各系列器件的pll可能功能上有差异,请查看相应器件的datasheet以及application notes,such as an251,an200,an156 etc  [2003-5-15 11:24:47]
[问: engineer] 如何根据容量大小来定购Cyclone器件? 
[答:Ivan] Cyclone device ordering codes are based on the number of available LEs in the device. All Cyclone device ordering codes begin with EP1C. The digits that follow indicate the number of LEs divided by a factor of 1,000. For example, the largest Cyclone device is the EP1C20 device and has 20,060 LEs.  [2003-5-15 11:26:32]
[问:zhdang] 在用到Cyclone器件时,遇到这样一个问题,在register-to-regiser Fmax中,如果两个寄存器的时钟是由同一个时钟不同分频得到的,他就会提示clock skew>data delay,怎么样解决这个问题 
[答:Rock] 再多时钟设计中,要在软件中做相应设置.在你的设计中,你首先要设置base clock(分频前的时钟)和derived clock(分频后).具体设置见:assignmeng->timing settings->clock.对于一个绝对时钟,quartus会在timing analysis 中报告他的Fmax,但两个不同时钟源的register 之间有path,在timing analysis 中就会报告skew,而没有Fmax.关于skew的意义,你可以从2rd register 的tsu 和th 参数入手.  [2003-5-15 11:26:37]
[问: anhong66] 1.在模拟电路设计中如何应用2.在图像处理方面的应用实例 
[答:Bill] 1.我们的芯片无法使用于模拟信号的直接处理,但是可以将模拟信号进行A/D转换后进行数字处理,再把结果通过D/A转换成模拟信号2.在图像方面我们芯片的应用很多,具体如图像传感器驱动时钟信号的产生,图像显示部分行场同步信号的产生,图像处理中一些变换的算法实现等等。  [2003-5-15 11:26:51]
[问:fanjia li2000@yah] 对多通道多任务的信息,处理器的处理能力及相应的缓冲存储器是很重要的,Nios 嵌入处理器在这方面的能力如何? 
[答:Ivan] Nios has provided customer instruction for customer to balance performance between hardware and software. It can implement some comlicated function with hardware to accelerate the performance. And Nios provide many register and buffer for you. we have already provided the example in our web for your evaluating.  [2003-5-15 11:27:14]
[问: engineer] Cyclone 器件是采用什么生产工艺制造? 
[答:Ivan] Cyclone devices are based on the same 1.5-V SRAM, 0.13um process used by Stratix devices. The process, which has been cost-optimized, benefits from all of the experience gained with APEX II and Stratix.  [2003-5-15 11:27:52]
[问:sales] Cyclone器件是否是基于Stratix的器件? 
[答:Ivan] No, Cyclone devices are not based on Stratix devices. Despite architectural similarities, the Cyclone device family is the industry抯 first PLD family to be designed specifically as a low-cost product. Unlike previous cost-reduced devices that are often re-packaged, re-priced high-density products, Cyclone devices were designed from the start with cost-savings in mind.  [2003-5-15 11:28:44]
[问:RED CLOUD] 如何用它实现计算机键盘扫描和控制电路? 
[答: Dawson] 具体的pld内部的电路实现,请跟Arrow相应的FAE沟通.010-85282030-427,021-53061871-369,0755-83592920-551  [2003-5-15 11:29:16]
[问:sun yaguang] 我主要使用MAXPLUS2软件进行开发,您能评价一下MAXPLUS2的IP核吗?如果我使用QUARTUS2,它还能支持FLEX10K系列芯片吗? 
[答:Ivan] Those megacore in MaxplusII are well tested and work efficiently, we recommend you to use it if you need that kind of function. that could improve your system performance. QII can support flex10k device.  [2003-5-15 11:29:35]
[问: luyang1.0] 请问cyclone系列的LE(逻辑单元)与逻辑门数之间的换算方法是什么? 
[答:Rock] Cyclone"s LE contains one 4 input LUT and one flopflop,carry chain and LUT chain.generally speaking,1 LE is equally to 12 gates counts.  [2003-5-15 11:29:41]
[问:limazoo] 请问,我从网上下载QUARTUS2.2 WEB EDITION 是否就已具备开发CYCLONE器件的能力了? 
[答:Dawson] 可以.  [2003-5-15 11:29:47]
[问:li.pei hong@net] 能否介绍一下nios套件中包含的IP 
[答:Edgar] NIOS has the following peripherals: Free peripherals: Avalon to AHB Bridges, Tri-State Bridges, SPI, UART, SDRAM controller, CS8900, LAN91c111, DMA, Interval Timer, PIO, etc...  Non-Free IP: CAN, I2C, 10/100/1G Ethernet MAC, 32-bit PCI, USB 1.1, 2.0, and many more cores from Altera and third parties.  For more info:  [2003-5-15 11:30:03]
[问:yuhw] demo board 的以太网口支持那些协议 
[答:Bill] 支持10M/100M 以太网协议  [2003-5-15 11:30:47]
[问:wen bin_RA27Q] 你前面展示的nios例子没有flash,那它的程序只有通过jtaq接口装入对吗?也就是说这个设计只能是演示不能在实际系统中应用对吗? 
[答:Ivan] Our Nios demo board do have Flash memory, you can run from both flash and JTAG port.  [2003-5-15 11:31:04]
[问:liujl] 在使用FPGA时与其他集成电路的使用条件有差别吗? 
[答: Dawson] 每类IC都有自己的工作环境,具体的参数请参看相应的datasheet.  [2003-5-15 11:32:11]
[问:huangjp] Which family Altera FPGA support Nios
[答:Bill] ACEX,FLEX,Stratix,Cyclone,APEX,APEX II,Mercury,Excalibur  [2003-5-15 11:32:16]
[问: huangjp] Cyclone开发板支持10/100M以太网,是在Cyclone内实现MAC功能还是另外外接MAC芯片 
[答:Ivan] We have IP core which can finish 10/100M Ethernet function implementing in Cyclone device, you just need to add a phy outside of cyclone.  [2003-5-15 11:33:10]
[问:spdut] 如何利用FPGA/CPLD实现晶振电路?如12MHz晶体,如何起振?50MHz呢? 
[答:Rock] almost all FPGA/CPLD does not incorporate oscillator,you must use external Oscillator and FPGA internal PLL to get the required frequence you want.though some fpga such as Cycone have internal oscillator,but it not for generall purpose ,it is only for fpga configuration.  [2003-5-15 11:33:53]
[问: tad2000] 对MAX7000系列与ACEX系列,ACEX系列要用EPC,在可编程接线JTAG上有什么不同
[答:Edgar] Since JTAG is a standard, therefore, there are not much differences.  Regarding EPC, since MAX is built by EEPROM technology, and ACEX is built by SRAM technology. MAX will not lose its contents after power down, but ACEX will lose its contents after power down.  EPC is a flash-like device to store the contents for ACEX during power-down and EPC will configure the ACEX after power-up.  [2003-5-15 11:34:02]
[问:niuniuo] FPGA的加密如何完成? 
[答:Bill] FPGA上电时需要外部提供配置数据,因此FPGA无法单独加密,但是你可以在你的系统中设计一块EPLD,并将EPLD加密,由此来防止整个设计被复制  [2003-5-15 11:34:36]
[问:wanjie .wang@ms] CPLD的IO驱动能力有多大? 
[答: Dawson] CPLD的IO最大能驱动50ma(7000B)  [2003-5-15 11:35:08]
[问: kevinyang] 我很感兴趣FPGA在软件无线电中的应用,有我成功案例? 
[答: Paulchan] Altera FPGA and CPLD have been successfully used in Software Defined Radio (SDR) applications. We have several leading insitutes and customers, but can not disclose details without their approval.Furthermore, Stratix"s embedded DSP Blocks is ideal for high performance applictions in wireless system design such as Turdo codec, correlators, FIR filters, etc...  [2003-5-15 11:35:18]
[问:zhanwei 3525@hot] 请问:Nios软嵌入RISC处理器在功能和开发上与一般的RISC处理器相比有那些优势,真的能吸引开发人员转向它吗? 
[答:Edgar] NIOS has the following advantages compare to standalone processor:  1.  NIOS is a soft core, can be ported to future FPGA architectures and will not stop production (other standalone will stop production).  2. NIOS provides wide variety of periphrals and customer can pick and choose different combinations and types of peripherals they really needed. e.g. 1 customer wants 20 UARTs, 1 MAC and a SDRAM controller, standalone processor cannot provide this.  NIOS is much more FLEXIBLE.   3.  NIOS can use FPGA logics for hardware acceleration.  i.e. user can built hardware acceleration with FPGA core logics and these logics can be called by the NIOS processor as a "Custom Instruction", hence dramatically increase the overal system performance.  4.  System designer don"t need to worry about software / hardware partition early in the cycle.  During the middle of the design cycle, if system designer discovered that the software / hardware combination cannot meet performance, they can re-arrange some proessing using FPGA hardware easily (such as using NIOS "Custom Instruction" hardware acceleration).  Or if a system designer discovered that that the software / hardware combination is an overkill of the current requirement, they can lower cost system cost by assigning some hardware processing using software instead.  In summary, NIOS has much more flexibility than standalone processor.  Regarding the development with NIOS, in terms of software, it is much the same as standalone processor.  In terms of its hardware architecture, Altera provide an easy to use SOPC builder where customer can pick and choose different options in an easy-to-use interface and the SOPC builder will generate the NIOS hardware in the FPGA for you.  [2003-5-15 11:35:24]
[问:2003z] 在编译的过程中,经常出现我所定制的管脚与编译的结果不一样请问怎样避免? 
[答:Ivan] You may need to notice the pin you assigned has the IO standard support which you want to use. The software should have the same result as you assignment.  [2003-5-15 11:35:38]
[问:qftmp] 我有一个要求200M实时采样系统设计,希望用FPGA或CPLD作高速存储管理和简单的数据过滤计算,通过仿真发现FPGA的速度有一定的问题,没有CPLD的仿真结果理想,希望能够提一些设计和选型方面的指点,还有仿真系统和仿真软件的选择。 
[答:Jing] Our latest and greatest FPGA"s are Stratix and Cyclone.  They all have different speed grades, C5, C6 and C7 for Stratix, and C6, C7 and C8 for Cyclone.  Lower number means a faster device.  Please try compile your design with these two devices to see if your fmax can be met.  To achieve the best result, a key guideline, is you should specify all your timing requirments in QuartusII.  The timing requirements should be precise and specific.  For example if you have 2 clock domains, one at 100Mhz, the other 200Mhz, then you should make tell QuartusII which clock is running @100Mhz, and which is @200Mhz.  Avoid just specify 200Mhz for both clocks.  Also, it"s the same for i/o timings, e.g. tsu and tco.  If you don"t have i/o timing requirement, then don"t specify any, if you have i/o timing requirement, then specify specifically.  You could also use LogicLock feature in QuartusII to bundle critical paths or critical module together so that their delay would be minimized.  Please refer to this document for further details: For simulation software, I can only tell you that what software we"ve seen engineers using, since they all have their strengths and weakness.  Some of this softwares are: For PC, ModelSim and ActiveHDL; for UNIX, VCS, VSS, and VerilogXL.  Please also check the following URL, where I believe you can find a lot useful documents.  [2003-5-15 11:35:39]
[问:Little Mouse] 能不能谈一谈fpga在手机的设计中是否有什么应用? 
[答:Bill] 我们曾有过用Cyclone芯片做一个外置的手机摄像头的应用实例,效果很好  [2003-5-15 11:36:22]
[问:wenedi] 用户能不能,用pll进行时钟倍频?如果能,怎么用;如果,不行,我们想在fpga内部实现高频信号如300兆的怎么办? 
[答:Ivan] Yes, customer can use the PLL to multiply the frequency, you can implement that funcation in QII, and the software also provide the check rule for you.  [2003-5-15 11:37:37]
[问:ecnan jing_EBY7E] 用CYCLONE CPLD设计的锁相环的精度有多高? 
[答:Edgar] phase shift down to 156ps.  [2003-5-15 11:37:52]
[问:明空] 当FPGA所用时钟较多时,可否将普通I/O脚作为时钟,需要什么特别的设置吗? 
[答:Bill] 可以,但是普通I/O做时钟内部的延时比较大,对于速度和延时要求不是很高的时钟信号是可以的,在设置上不需要什么特殊设置  [2003-5-15 11:38:24]
[问:daryl] 请详细解释一下Cyclone器件"专用SDRAM接口电路” 
[答: Dawson] 请参看CYCLONE的datasheet和an256文档.  [2003-5-15 11:38:52]
[问:writer] NIOS目前有无RTOS支持? 
[答:Rock] sure!NIOS support the following RTOS:Accelerated Technology Nucleus PLUS Real-time operating system (RTOS). MiSPO Co. Ltd. NORTi Compact Edition  RTOS with very small memory footprint; μITRON-compliant Microtronix Datacom Linux Development Kit by Microtronix Add-on development kit; provides a μClinux port to the Nios embedded processor Micrium μC/OS-II Highly portable, scalable, preemptive, real-time, multitasking kernel Shugyo Design Technologies KROS operating system RTOS with very small memory footprint; for more information,refer to:  [2003-5-15 11:39:01]
[问: sbntulip] 用NOIS构建一个最简单的微控制器(实现8位单片机的功能,2个定时器,一个UART,256ram,2k的rom)的方法,包括采用什么器件,开发板。开发板怎样购买,参考价格。采用的FPGA(CPLD)的参考价格?多谢 
[答:Singer] Dears ,You may buy the Nios Board from us , kindly send email to me at or phone to 0755 83592920 (556) of Qiupei .  Thanks .  [2003-5-15 11:39:35]
[问:ljp] 什么是软核处理器?它的速度有通常的处理器快吗?软件许可证费用多少? 
[答:Ivan] The soft processor is different from hard core, which implement with a couple of HDL file, and can be used in any device of altera families. And the performance depends on the device families you select. The customer doesn"t need ot be charged for the core license, it"s free core.  [2003-5-15 11:40:06]
[问:ljp] FPGA和CPLD是两种不同的PLD,和其它供应商相比,Altera在那哪方面技术占优势?CPLD或FPGA? 
[答: Paulchan] Altera places strong empthasis on both FPGA and CPLD technology, as evident in the new Stratix and Cyclone products which is manufactured on 130nm all cupper process technology. For CPLD Altera will announce a new family soon.Also very importantly, besides the silicon, Altera also invest heavily into the development software and IP cores, to enable a complete SOPC solution for our customers.  [2003-5-15 11:41:41]
[问:sales] Cyclone器件支持什么类型的外接存储器接口?数据速度如何? 
[答:Ivan] Cyclone devices, similar to the Stratix device family, can interface with single data rate (SDR) and double data rate (DDR) SDRAM devices, as well as fast cycle memory devices (FCRAM) using a dedicated, speed-optimized interface. Cyclone devices can seamlessly access these devices at speeds up to 266 megabits per second (Mbps) using a 133-MHz clock.  [2003-5-15 11:42:17]
[问:ljp] 请介绍一下CPLD和FPGA的优点和缺点。它们的应用范围有何不同?可以互相替代吗? 
[答:Ivan] CPLD is eeprom structure, and FPGA is sram structure. The former doesn"t need the configured device, and FPGA needs. Commanly, FPGA has more logic element than CPLD, which is used for large and complicated logic function.  [2003-5-15 11:42:43]
[问:love lydaidai] 我从前使用MaxPLUSII,现在使用QUARTUS。QUARTUS的功能的确比MAXPLUS强的多,可是同样器件和同样规模的设计编译、综合和不限的速度要慢的多。为什么? 
[答:Edgar] Quartus II 3.0 has dramtically improved compilation performance for traditional MaxPlusII-supported devices.  Quartus II 3.0 is scheduled to be released on June.  [2003-5-15 11:42:58]
[问:sales] Cyclone 器件提供什么样的系统时钟管理解决方案? 
[答:Ivan] Cyclone devices provide a global clock network and phase-locked loops (PLLs) with on-and-off-chip capabilities for a complete system clock management solution.  [2003-5-15 11:43:19]
[问:hnfhc] 现在FPGA和CPLD具有很强大的功能,在某种程度上可以替代CPU及其外围电路。但如果用FPGA代替CPU进行控制,编的程序将会非常庞大,肯定不比熟悉CPU的指令并用汇编语言或C语言编程来得方便。FPGA要想取代CPU的角色,必须提供更为简便的(例如提供模块化的程序包)编程方法,ALTERA做过这方面的工作吗? 
[答:Jing] Yes.  Our SOPC Builder exactly addresses your concern.  NIOS processor core and its peripherals such timer, uart, etc can be directly instantiated from graphic user interface.  The conncections and drivers are automatically handled by the software.  Please refer to SOPC Builder Data Sheet in this link:  [2003-5-15 11:43:52]
[问:wanjie .wang@ms] 使用MUXPLUS 软件。自己带的VHDL编译器和外部的第三方编译器相比有什么区别。 
[答:Ivan] Both MPII and third party tools can synthesis VHDL and have good performance, the customer can use it as one like.  [2003-5-15 11:44:03]
[问:wenedi] FPGA内部有没有可以直接利用的锁相环,类似于硬件乘法器 
[答:Edgar] Yes, Cylone has maximum of two analog PLLs in its core.  [2003-5-15 11:44:22]
[问:zbear] 有没有视频增强类的IP核或相关产品? 
[答:Dawson] Stratix具有多个dsp硬核和大量的存储单元(最多到10mb),适用高端的视频处理.cyclone具有高速的存储单元,和低的成本,结合32位的处理器nios,可用于具有大量的视频产品的开发.我们也有相应的视频IP核,请参看 &technology=DSP&keywords=&nav3=signalprocess [2003-5-15 11:45:01]
[问:Little Mouse] 有办法对FPGA的电路进行调试吗?FPGA中的设计不像程序,可以进行调试,比如单部调试、设置断点等等。如果发现FPGA的设计不能满足要求,那么有什么好办法可以发现其中的问题呢?谢谢 
[答:Ivan] You can simulate the logic function you have made, both altera software and third party tools can provide simulate function. Timing simulation can test all the question of your design, that"s to say, if your design passed the timing simulation, the logic fuction should work fine on board.  [2003-5-15 11:46:46]
[问:zhang kun402] 现在的CPLD/FPGA可以支持I2C总线技术吗?应该如何开发? 
[答:Rock] cpld/fpga 可以作为I2C 协议的一个平台或载体,因此你可以据i2c协议进行cpld/fpga .流程如下:根据协议编写源代码(原理图或VHDL或verilog HDL)->进行功能仿真(在Altera 的MAXPLUX2 或Quartus2软件里)->编译,布局布线->时序分析,时序仿真->下载,板级验证.  [2003-5-15 11:47:27]
[问: mobile_cat] 1。不知CPLD是否可以进行复杂的延时?2。CPLD是否可以做到倍频? 
[答: Dawson] CPLD可以做复杂的延时处理,不过为了你设计的系统有更好的性能,我们推荐有同步设计.CPLD可以通过异步设计做倍频.  [2003-5-15 11:47:52]
[问:eebyte] MAX3000系列是基于EEPROM的配置方式吗? 
[答:Rock] MAX3000A is eeprom based cpld,so you can write the programing file to each eeprom  cell so as to enable your custom fuction of the cpld.  [2003-5-15 11:51:06]
[问:dfli] 如何针对具体的应用选择cpld还是fpga,比如单片机与图形点阵lcd的接口,包含字模和控制? 
[答:Jing] The basic difference between cpld and fpga are: 1. cpld is eeprom based, so it doesn"t loose programming file upon power-off, while fpga needs to be programmed at each power-up2. cpld is usually small in logic density and simple features, typically used for simple control logic, power management or i/o expansion. Fpga can reach very high logic density, and supple advanced features such as pll, rams, dsp, advanced i/o"s such as differential and referenced-voltaged i/o"s, so they can carry heavy and complicated logic designs.  [2003-5-15 11:51:31]
[问:limazoo] 想在EP1C2上集成12以上的独立ROM,每个ROM为64X8,如何实现? 
[答: Dawson] 是否应该是EP1C12?你可通过我们的Megawizard中的ROM模块来定制.  [2003-5-15 11:51:36]
[问:holoman] Altera公司是否有把模拟信号处理比如AD/DA之类的一些模块加入FPGA/CPLD的产品? 
[答:Jing] This is in our future roadmap, but we cannot release further info on this yet.  [2003-5-15 11:52:46]
[问: holoman] NOIS是否是可裁减的? 
[答:Ivan] Yes, user can customize their owh soft processor core. which can implement in QII.  [2003-5-15 11:53:57]
[问:feng haihong] 请重点讲解低功耗设计,以及FPGA、CPLD功耗的计算,谢谢 
[答: Dawson] 功耗跟芯片的工艺及机构有关.我们的QuartusII可计算出你设计相应的功耗.你也可参看an74和cyclone的功耗计算 utilities/cyc-design_utilities.html  [2003-5-15 11:54:55]
[问:stephn wang@msik] 当采用FPGA 设计一个PCI_X 的BUS MASTER ,要实现一个PCI 的全部功能,请问状态机如何设计,FRAME IRDY PAR 等信号如何产生?谢谢 
[答:Bill] 此问题比较复杂,需要对你的设计作进一步的了解,请保持和我们的FAE联系,可以给你做进一步的支持。  [2003-5-15 11:55:14]
[问: wjerryking] FPGA和CPLD在电机调速方面有些什么优势或不足? 
[答:Jing] CPLD is easy and cheap to use.  FPGA can handle more complicated logic and therefore more flexible and powerful.  [2003-5-15 11:56:11]
[问: bigfathui] 低成本的FPGA和CPLD的多电源方案如何解决的? 
[答:Rock] concering low cost cpld/cpld,you can either choose linear(costeffective) or switch power (high efficiency) according to your system requirement(such as used IO count,Fmax,how much IO banks,IO standard,etc to calculate the power consumption of the cpld/fpga).  [2003-5-15 11:56:12]
[问:qin] CPLD的内部IP Core的结构是怎样的? 
[答:Ivan] IP core is some HDL file which implement some commen function, which is made by altera or some other third party company. Use IP core can help you to reduce design time and faster your product face to market.  [2003-5-15 11:56:32]
[问:qin] 新一代的FPGA的内部宏单元的物理结构是怎样的? 
[答:Edgar] Basically, each logic element contains one 4-input LUT (look-up-table, like a ROM) and a register and associated logics.  You can find the logic element architecture in page 9 of the Cyclone datasheet available from  [2003-5-15 11:57:22]
[问: li.peihong @netease .com] 目前可运行nios 的fpga有哪些具体的型号?nios需要的fpga基本参数有哪些,如寄存器数量等? 
[答:Ivan] Commenly, the standard NIOS need 1600 LES, which can be place in any altera device if it has enough resource.  [2003-5-15 11:59:09]
[问:zjli733] cpld fpga的开发都可以使用maxplus,quartus也是开发FPAG? 
[答:Ivan] Both MPII and QII can develop CPLD and FPGA.  [2003-5-15 11:59:41]
[问:Bear zeng] EP10K300BEC652-3内部有没有PLL? 
[答:Jing] Yes in EP10K300BEC652-3X, if just EP10K300BEC652-3, then no.  [2003-5-15 12:00:00]
[问:cqz@] 能否在MAXPLUSII里调用MODELSIM进行时序仿真?怎么进行呢? 
[答:Edgar] MAXPLUSII cannot call modelsim automatically, this is something that Quartus II can do.  However, you can ask MAXPLUS II to generate a netlist for Modelsim simulation.  Please turn on the Netlist-Writer in MAXPLUS II for netlist generation.  [2003-5-15 12:00:15]
[问:leleg] 请问Quartus 3.0支持nios吗? 
[答:Jing] Yes.  [2003-5-15 12:01:52]
[问:gmwgz] 请问现有CPLD有无集成MCS51内核的产品? 
[答:Rock] CPLD is smaller than can implenment it in all ALTERA FPGA such as Cyclone.With altera roylty free Nios cpu,you can replace the 51 with Nios cpu core to get higher performance.  [2003-5-15 12:03:01]
[问:sbntulip] 请问如何同时构建一个基本的32位的控制器和PCI控制器,可以选用什么器件? 
[答: Dawson] 我们有pci controller的ip core,根据其他的逻辑的大小,可选择cyclone中的相应的器件.具体的选择,你也可跟Arrow的fae联系:010-85282030-427,021-53061871-369,0755-83592920-551  [2003-5-15 12:03:36]
[问:ljp] 请介绍一下Nios处理器所增加的ISA接口的功能和用途。 
[答:Ivan] Nios can add standard ISA periphery, which is compatible to other standard ISA interface.  [2003-5-15 12:04:25]
[问:ljp] 与Nios系统相匹配的外围接口有哪些? 
[答:Ivan] You can find the periphery list in the QII software, you can open SOPCbuilder to view and select.  [2003-5-15 12:05:18]
[问:leonqin] 用EP1C6最慢一档是否可实现133MHz的SDRAM控制器? 
[答:Dawson] 可实现sdram 控制器,但很难达到133m的时钟频率.  [2003-5-15 12:05:29]
[问: zhaoshi9@] 在设计中,为了少用芯片,有时不得已要在一个芯片中用到多时钟,或行波时钟,这将带来系统的不稳定,请问有无好办法解决? 
[答:Rock] the most popular FPGA like Cycone have adequate clok resorce to meet you has up to 8 global colk and 4 dedicate clock input plus some dual purpose clock input in.So,in muti-clock design,Cyclone can help improve the stability of your design.  [2003-5-15 12:07:33]
[问:huang guonan] 请问什么型号的CPLD或FPGA可以用作功驱动接口,如驱动LCD 
[答: Dawson] 可选择max3000a系列,通常epm3064足够.但也要看你具体逻辑的大小,请最好咨询Arrow的fae:010-85282030-427,021-53061871-369,0755-83592920-551  [2003-5-15 12:08:17]
[问:ciyanke] CPLD中是否所有触发器的时钟输入都必须使全局时钟信号?一般综合的电路可以占用到总容量的百分之多少? 
[答:Edgar] Not necessarily, normal logics can drive DFF in the CPLD, however, user has to be carefully with the extra clock skew induced by normal logics routing.  Global clock is still the best to ensure minimum amount of clock skew.  Recent survey from customer (we have > 14000 customer worldwide) is that most circuities can occupy over 90% of the chip"s resouces.  This is mainly due to the constant improvement of our software routing algorithm in our Quartus II software.  [2003-5-15 12:08:26]
[问:明空] 哪种FPGA可以直接支持5V PCI ,不用串接电阻? 
[答:Edgar] Altera FLEX devices  [2003-5-15 12:10:07]
[问:lu_six] nios好像不能支持vxworks,是吧?对此是否有计划。 
[答:Ivan] Yes, Nois doesn"t support VXworks, but it does support other RTOS, such as Linux...  [2003-5-15 12:10:30]
[问:700301@ btamail.] nois与其他微处理器的内部结构有何异同?谢谢!!! 
[答:Ivan] Nios is design by Altera ourselves, it base on RISC structure.  [2003-5-15 12:11:39]
[问:qin] 现在的CPLD门到门的延时有多大? 
[答: Dawson] 每个cpld的延时可能都不同.目前最快到3.5ns  [2003-5-15 12:12:28]
[问:zjli733] 如果一个单片机核已经下载到FPGA中,如何使用呢,就像硬件单片机一样? 
[答:Ivan] Yes, you can use as standard microprocess, we provide serial port as the debug  interface.  [2003-5-15 12:12:37]
[问:qin] 用FPGA设计的DSP与产品化的DSP如TMS320VC5402PGE100相比有何优劣? 
[答:Bill] FPGA设计的DSP模块一个嵌入在fpga之中的ipcore,只能实现某个特定的DSP功能,不象TMS320是一个处理器可以用软件来实现不同的dsp算法,所以,用FPGA实现DSP可以提供近似于纯硬件实现的性能,在你需要修改的时候也可以在FPGA上做一些修改而不用改动电路,虽然TMS320可以很灵活的改动其功能,但是性能远远不如FPGA实现的DSP。  [2003-5-15 12:13:36]
[问:qin] 用FPGA设计CPU,DSP有哪些技巧? 
[答:Ivan] You can find some useful help from our application documentation, and we have SOPC builder and DSP builder software to help your design.  [2003-5-15 12:13:43]
[问:love lydaidai] 请问Cyclone系列和传统的低成本ACEX系列器件相比有何不同 
[答:Rock] they are different in process and architecture.Cyclone is based on 0.13u and ACEX is based on 0.22u-result in lower cost.Cyclone"s architecture is superior to ACEX,result in higher performance .  [2003-5-15 12:14:41]
[问: zhdang] 在应用Cyclone,进行时序分析register-to-register fmax时发现如果两个regiser的时钟是由同一个时钟产生的并不完会相同的CLK,就会提示此高频时钟在这两个register之间clock skew>data delay,请问这是由什么引起的,有什么解决办法吗 
[答:Ivan] You may contact our distributor to help on this, you need to adjust some QII setting to fix it.  [2003-5-15 12:14:48]
[问:limazoo] 在CYCLONE 中设计RAM时,需要有时钟推动,也即只有时钟上升沿才能能驱动地址,在数据端输出数据.如何能实现象ACEX系列中的RAM,地址有效后,在数据端马上得到有效数据输出? 
[答: Dawson] cycone支持同步的ram设计.要转换异步到同步,可参看an210  [2003-5-15 12:15:51]
[问:Bear zeng] 使用NIOS2.11时,发现使用printf打印大量信息到串口时,很容易使NIOS出现没有响应。不知道是不是程序跑飞还是什么原因? 
[答:Ivan] You can contact our distributo to help you debug the issues.  [2003-5-15 12:15:59]
[问:niuniuo] 如何得到ALTERA公司提供的IP核?用户有没有可能自己编写IP核?用什么工具编写? 
[答:Rock] you can download it form Altera website for evaluation purpose,then you can decide to buy it or can also write your own IP core ,but you must encrypt it by your self.the later version Quartus may help you in building your personal IP core.  [2003-5-15 12:18:30]
[问: tomsoft] 能否介绍一下HardCopy?如何实现?成本和Cyclone相比如何? 
[答:Edgar] HardCopy is the convertion of FPGA to ASIC chip, unused routings in the FPGA are taken out to reduce the chip die size, hence lower the chip cost.  Altera will handle the whole convertion process.  Customer just need to finish the design of the selected FPGA that support HardCopy and give Altera the netlist for the conversion.  For more info:  HardCopy is more for high-density FPGA such as Stratix.  Cyclone is already at the price point and density level that can directly compete with wide range of ASIC density hence no HardCopy is needed for Cyclone.  In summary, HardCopy addresses high-density, middle-to-high volumn applications, whereas, Cyclone addresses middle-to-low density, high volumn applications.  [2003-5-15 12:18:52]
[问: ciyanke] 对于多电压的FPGA芯片,I/O口的电压范围为3.3V或者5V,可否使用两者之间的电压值,例如4V? 
[答:Rock] it is not recommended.  [2003-5-15 12:19:40]
[问: ciyanke] 如何实现FPGA的双向口?内部是否有可以直接使用的双向口? 
[答:Rock] each io of ALTERA FPGA have internal bidirectional buffer.However,you need to configure it in your souce design correctly.or you can directly call ALTERA lpm.  [2003-5-15 12:22:13]
[问:明空] 想对某个信号进行大约两个逻辑门的延迟,应该怎么做,加两个非门会被优化掉? 
[答:Bill] 可以用LCELL  [2003-5-15 12:23:14]
[问:sanhu] Cyclone系列芯片管脚是否有静电保护功能? 
[答:Rock] yes.  [2003-5-15 12:23:18]
[问: xingstar] How about 64-bit,66MHz PCI add into NIOS system? 
[答:Bill] 目前还只支持32bit的PCI  [2003-5-15 12:24:32]
[问:lu_six] 有没有管脚比较少(比如44),但是容量比较大(有100个以上的宏单元)的cpld。有这样的fpga也行。 
[答:Rock] no .  [2003-5-15 12:24:41]